Patents by Inventor Shekar Mallikarjunaswamy
Shekar Mallikarjunaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10497697Abstract: A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the first finger and second finger extending in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The semiconductor regions in a first portion of the first and second fingers form a silicon controlled rectifier and the semiconductor regions in a second portion of the first and second fingers form a P-N junction diode.Type: GrantFiled: October 16, 2018Date of Patent: December 3, 2019Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventor: Shekar Mallikarjunaswamy
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Publication number: 20190304965Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 10373947Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: GrantFiled: July 25, 2018Date of Patent: August 6, 2019Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Publication number: 20190157257Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.Type: ApplicationFiled: January 4, 2019Publication date: May 23, 2019Inventor: Shekar Mallikarjunaswamy
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Publication number: 20190123039Abstract: A transient voltage suppressor (TVS) circuit includes a first finger and a second finger of semiconductor regions arranged laterally along a first direction on a major surface of a semiconductor layer, the first finger and second finger extending in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The semiconductor regions in a first portion of the first and second fingers form a silicon controlled rectifier and the semiconductor regions in a second portion of the first and second fingers form a P-N junction diode.Type: ApplicationFiled: October 16, 2018Publication date: April 25, 2019Inventor: Shekar Mallikarjunaswamy
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Publication number: 20190074274Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.Type: ApplicationFiled: November 1, 2018Publication date: March 7, 2019Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 10224411Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.Type: GrantFiled: May 30, 2017Date of Patent: March 5, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Shekar Mallikarjunaswamy, Francois Hebert
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Patent number: 10211199Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.Type: GrantFiled: September 28, 2017Date of Patent: February 19, 2019Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventor: Shekar Mallikarjunaswamy
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Patent number: 10157904Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.Type: GrantFiled: March 31, 2017Date of Patent: December 18, 2018Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Publication number: 20180342499Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: ApplicationFiled: July 25, 2018Publication date: November 29, 2018Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 10141300Abstract: A transient voltage suppressor (TVS) circuit includes a P-N junction diode and a silicon controlled rectifier (SCR) formed integrated in a lateral device structure of a semiconductor layer. The lateral device structure includes multiple fingers of semiconductor regions arranged laterally along a first direction on a major surface of the semiconductor layer, defining current conducting regions between the fingers. The current paths for the SCR and the P-N junction diode are formed in each current conducting region but the current path for the SCR is predominantly separated from the current path for the P-N junction diode in each current conducting region in a second direction orthogonal to the first direction on the major surface of the semiconductor layer. The TVS device of the present invention realizes low capacitance at the protected node. The TVS device is suitable for protecting data pins of an integrated circuit, especially when the data pins are used in high speed applications.Type: GrantFiled: October 19, 2017Date of Patent: November 27, 2018Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventor: Shekar Mallikarjunaswamy
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Patent number: 10121668Abstract: A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.Type: GrantFiled: November 16, 2017Date of Patent: November 6, 2018Assignee: Alpha and Omega Semiconductor, Inc.Inventor: Shekar Mallikarjunaswamy
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Patent number: 10109625Abstract: A power integrated circuit and a method of forming includes forming a first body region of a first conductivity type in a first deep well of a second conductivity type. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region is formed by performing first and second ion implantations of dopants of the first conductivity type and using second implant energy greater than the first implant energy.Type: GrantFiled: November 6, 2017Date of Patent: October 23, 2018Assignee: Alpha and Omega Semiconductor, Inc.Inventor: Shekar Mallikarjunaswamy
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Publication number: 20180286853Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.Type: ApplicationFiled: September 28, 2017Publication date: October 4, 2018Inventor: Shekar Mallikarjunaswamy
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Publication number: 20180286852Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 10062682Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: GrantFiled: May 25, 2017Date of Patent: August 28, 2018Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 10038062Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.Type: GrantFiled: August 20, 2017Date of Patent: July 31, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Shekar Mallikarjunaswamy, Madhur Bobde
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Patent number: 10020369Abstract: A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode; and alternating N-type and P-type regions formed in the drain drift region with higher doping concentration than the drain-drift regions to form a super-junction structure in the drain drift region.Type: GrantFiled: February 1, 2017Date of Patent: July 10, 2018Assignee: Alpha and Omega Semiconductor IncorporationInventor: Shekar Mallikarjunaswamy
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Patent number: 10008598Abstract: In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.Type: GrantFiled: September 12, 2015Date of Patent: June 26, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Shekar Mallikarjunaswamy, John Chen, Yongzhong Hu
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Publication number: 20180122799Abstract: A power integrated circuit and a method of forming includes forming a first body region of a first conductivity type in a first deep well of a second conductivity type. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region is formed by performing first and second ion implantations of dopants of the first conductivity type and using second implant energy greater than the first implant energy.Type: ApplicationFiled: November 6, 2017Publication date: May 3, 2018Inventor: Shekar Mallikarjunaswamy