Patents by Inventor Shelagh Callahan

Shelagh Callahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070006281
    Abstract: An apparatus and method for platform and device independent identity manageability. In one embodiment, the method includes validation of a manageable identity (MID) held within trusted storage of a user platform according to a user request to move the MID to a target platform. Once the MID is validated, available resources of the target platform are verified according to resource requirements of the MID. Once verified, the MID may be moved from the user platform to trusted storage provided by the target platform. In one embodiment, a platform-independent MID may be established that may be moved from a user platform to a non-compatible target platform, such that the platform-independent MID is not constrained to just one single platform. Other embodiments are described and claimed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Sameer Abhinkar, Selim Aissi, Jane Dashevsky, Abhay Dharmadhikari, Benjamin Matasar, Mrudula Yelamanchi, Scott Blum, Shelagh Callahan
  • Publication number: 20060068758
    Abstract: A method of securing a local link may involve exchange of initiation messages and negotiation of ciphersuites across a local link. The method then transmits a server authentication and receives a client authentication. Upon validation of the server and client authentication, information from the cipher is used to encrypt communications across the local link. In addition, there is a method of providing intra-platform security. The method performs authentication between two endpoints on a platform and then generates keys between the two endpoints to form a trusted tunnel. The keys are used to encrypt communications between the endpoints.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Abhay Dharmadhikari, Mrudula Yelamanchi, Jane Dashevsky, Benjamin Matasar, Selim Aissi, Jose Puthenkulam, Shelagh Callahan
  • Patent number: 5623610
    Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: April 22, 1997
    Assignee: Intel Corporation
    Inventors: Shaun Knoll, Jeff C. Morriss, Shelagh Callahan, Ajay V. Bhatt, Sudarshan B. Cadambi
  • Patent number: 5615404
    Abstract: A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: March 25, 1997
    Assignee: Intel Corporation
    Inventors: Shaun Knoll, Jeff C. Morriss, Shelagh Callahan, Ajay V. Bhatt, Puthiya K. Nizar, Richard M. Haslam, Andrew M. Volk, Sudarshan B. Cadambi