Abstract: An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.

Abstract: An integrated circuit applied in a deep neural network is disclosed. The integrated circuit comprises at least one processor, a first internal memory, a second internal memory, at least one MAC circuit, a compressor and a decompressor. The processor performs a cuboid convolution over decompression data for each cuboid of an input image fed to any one of multiple convolution layers. The MAC circuit performs multiplication and accumulation operations associated with the cuboid convolution to output a convoluted cuboid. The compressor compresses the convoluted cuboid into one compressed segment and store it in the second internal memory. The decompressor decompresses data from the second internal memory segment by segment to store the decompression data in the first internal memory. The input image is horizontally divided into multiple cuboids with an overlap of at least one row for each channel between any two adjacent cuboids.

Abstract: An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.

Abstract: A folded butterfly module performs a radix-22 butterfly operation, and includes: a buffer operable to store first and second to-be-stored data and output first and second stored data; a first multiplexer operable to output one of the second stored data and input data as first selection data; a butterfly operator performing a radix-2 butterfly operation on the first stored data and the first selection data to generate operation data and the second to-be-stored data; a second multiplexer operable to output one of the input data and the operation data as the first to-be-stored data; a third multiplexer operable to output one of the operation data and the second stored data as second selection data; and a multiplier generating output data that equal a product of the second selection data and twiddle data.

Abstract: A folded butterfly module performs a radix-22 butterfly operation, and includes: a buffer operable to store first and second to-be-stored data and output first and second stored data; a first multiplexer operable to output one of the second stored data and input data as first selection data; a butterfly operator performing a radix-2 butterfly operation on the first stored data and the first selection data to generate operation data and the second to-be-stored data; a second multiplexer operable to output one of the input data and the operation data as the first to-be-stored data; a third multiplexer operable to output one of the operation data and the second stored data as second selection data; and a multiplier generating output data that equal a product of the second selection data and twiddle data.