Patents by Inventor Shen Luan
Shen Luan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11209422Abstract: The invention provides methods for rapid and quantitative extraction and detection of coenzyme Q10 in a sample readily adaptable to high throughput screening methods. The invention further provides reagents and kits for practicing the methods of the invention.Type: GrantFiled: September 21, 2018Date of Patent: December 28, 2021Assignee: Berg LLCInventors: Shen Luan, Niven Rajin Narain, Rangaprasad Sarangarajan, Nikunj Narendra Tanna
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Publication number: 20190257820Abstract: The invention provides methods for rapid and quantitative extraction and detection of coenzyme Q10 in a sample readily adaptable to high throughput screening methods. The invention further provides reagents and kits for practicing the methods of the invention.Type: ApplicationFiled: September 21, 2018Publication date: August 22, 2019Inventors: Shen LUAN, Niven Rajin Narain, Rangaprasad Sarangarajan, Nikunj Narendra Tanna
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Patent number: 10114013Abstract: The invention provides methods for rapid and quantitative extraction and detection of coenzyme Q10 in a sample readily adaptable to high throughput screening methods. The invention further provides reagents and kits for practicing the methods of the invention.Type: GrantFiled: May 25, 2016Date of Patent: October 30, 2018Assignee: Berg, LLCInventors: Shen Luan, Niven Rajin Narain, Rangaprasad Sarangarajan, Nikunj Narendra Tanna
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Publication number: 20170097336Abstract: The invention provides methods for rapid and quantitative extraction and detection of coenzyme Q10 in a sample readily adaptable to high throughput screening methods. The invention further provides reagents and kits for practicing the methods of the invention.Type: ApplicationFiled: May 25, 2016Publication date: April 6, 2017Inventors: Shen Luan, Niven Rajin Narain, Rangaprasad Sarangarajan, Nikunj Narendra Tanna
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Patent number: 9360454Abstract: The invention provides methods for rapid and quantitative extraction and detection of coenzyme Q10 in a sample readily adaptable to high throughput screening methods. The invention further provides reagents and kits for practicing the methods of the invention.Type: GrantFiled: March 1, 2013Date of Patent: June 7, 2016Assignee: Berg LLCInventors: Shen Luan, Niven Rajin Narain, Rangaprasad Sarangarajan, Nikunj Narendra Tanna
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Publication number: 20140049329Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.Type: ApplicationFiled: August 15, 2012Publication date: February 20, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Luan Liu
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Patent number: 8019022Abstract: An embodiment of a clock and data recovery circuit comprising a first clock and data recovery circuit with high bandwidth and a second clock and data recovery circuit with low bandwidth is disclosed. The first clock and data recovery circuit with high bandwidth receives a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein a second data rate X bps of the first signal and the second signal is half of a first data rate of the data signal. The second clock and data recovery circuit with low bandwidth receives and reduces jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal.Type: GrantFiled: February 4, 2008Date of Patent: September 13, 2011Assignees: Mediatek Inc., National Taiwan UniversityInventors: Shen-luan Liu, Che-Fu Liang, Sy-Chyuan Hwu
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Patent number: 7902900Abstract: A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.Type: GrantFiled: November 6, 2009Date of Patent: March 8, 2011Assignees: Mediatek Inc., National Taiwan UniversityInventors: Shen-luan Liu, Chih-Hung Lee
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Patent number: 7636003Abstract: A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.Type: GrantFiled: March 20, 2007Date of Patent: December 22, 2009Assignees: Mediatek Inc., National Taiwan UniversityInventors: Shen-luan Liu, Chih-Hung Lee
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Patent number: 7592847Abstract: A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.Type: GrantFiled: September 26, 2007Date of Patent: September 22, 2009Assignee: Mediatek Inc.Inventors: Shen-luan Liu, Che-Fu Liang, Hsin-Hua Chen