Abstract: A version-compatible data processing system including an application program for user interaction with stored data, the application program including means for generating, storing, and retrieving data files that each have an array of the data objects, the means for retrieving including means for determining recognition of the object type of each object, and means for retrieving each unrecognized object without processing.

Abstract: An integrated data processing system including an application program that has means for generating and editing data files, each data file including an array of data objects that each have an associated object address, and object content being any of a number, a formula, a date, a text, media data, and binary data other than a number, a formula, a date, or a text, each object address in a data file being unique with respect to that data file.

Abstract: An integrated multi-application data processing system including means for generating, storing, and retrieving data files, each data file having a multi-dimensional array of data cells, and a program framework providing a common user interface for at least one application program for user interaction with one or more of the data files. Each of the data cells, which can contain a single data object that includes an object type code and object content, has a unique multi-dimensional cell address with respect to all cells in data files generated by the system. The object content can be self-contained and/or defined in terms of object content of other data objects, and the object type code is indicative of the object content being any of a number, a formula, a date, a text, a page, media data, and binary data other than a number, a formula, a date, or a text. The media data type can be at least a picture, a sound track, or a video clip.

Abstract: The present invention is memory access system suitable for use in a computer system having M memory banks and N masters. The memory access system comprises a separate paged interleaved controller associated with each of the M memory banks. Each of the paged interleaved controllers comprises a bank arbiter and a bank controller. The bank arbiter associated with each memory bank receives requests from the N masters and subjects them to a request-halt protocol. The request-halt protocol executed by each arbiter prioritizes among a plurality of current requests by said masters for the same memory bank. Each arbiter insures that a current request generated by a master will not be granted if the master has a previous request that has not been granted by another arbiter. This insures that the requests of each master are granted in the order in which the requests are made.