Patents by Inventor Sheng C. LI
Sheng C. LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862552Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.Type: GrantFiled: January 3, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
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Patent number: 11824013Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.Type: GrantFiled: August 15, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Lauren A. Link, Andrew J. Brown, Sheng C. Li, Sandeep B. Sane
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Patent number: 11676891Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: June 30, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Patent number: 11622448Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.Type: GrantFiled: July 8, 2019Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Brandon C. Marin, Tarek Ibrahim, Srinivas Pietambaram, Andrew J. Brown, Gang Duan, Jeremy Ecton, Sheng C. Li
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Patent number: 11610706Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.Type: GrantFiled: January 12, 2018Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Sai Vadlamani, Prithwish Chatterjee, Rahul Jain, Kyu Oh Lee, Sheng C. Li, Andrew J. Brown, Lauren A. Link
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Patent number: 11581271Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.Type: GrantFiled: March 14, 2019Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Rahul Jain, Kyu-Oh Lee, Islam A. Salama, Amruthavalli P. Alur, Wei-Lun K. Jen, Yongki Min, Sheng C. Li
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Publication number: 20230022714Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: September 29, 2022Publication date: January 26, 2023Inventors: Hongxia Feng, Dungying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20220310518Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Inventors: Haobo CHEN, Xiaoying GUO, Hongxia FENG, Kristof DARMAWIKARTA, Bai NIE, Tarek A. IBRAHIM, Gang DUAN, Jeremy D. ECTON, Sheng C. LI, Leonel ARANA
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Publication number: 20220230951Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Applicant: Intel CorporationInventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li
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Patent number: 11335632Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.Type: GrantFiled: December 28, 2017Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li
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Publication number: 20220130748Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.Type: ApplicationFiled: January 3, 2022Publication date: April 28, 2022Applicant: INTEL CORPORATIONInventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
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Patent number: 11251113Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.Type: GrantFiled: December 27, 2017Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
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Publication number: 20210327800Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
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Publication number: 20210273036Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Applicant: Intel CorporationInventors: Brandon C. Marin, Tarek Ibrahim, Prithwish Chatterjee, Haifa Hariri, Yikang Deng, Sheng C. Li, Srinivas Pietambaram
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Patent number: 11088062Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: July 19, 2017Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20210050306Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.Type: ApplicationFiled: August 15, 2019Publication date: February 18, 2021Applicant: INTEL CORPORATIONInventors: Lauren A. Link, Andrew J. Brown, Sheng C. Li, Sandeep B. Sane
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Publication number: 20210014972Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.Type: ApplicationFiled: July 8, 2019Publication date: January 14, 2021Inventors: Brandon C. MARIN, Tarek IBRAHIM, Srinivas PIETAMBARAM, Andrew J. BROWN, Gang DUAN, Jeremy ECTON, Sheng C. LI
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Publication number: 20200294938Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Inventors: Rahul JAIN, Kyu-Oh LEE, Islam A. SALAMA, Amruthavalli P. ALUR, Wei-Lun K. JEN, Yongki MIN, Sheng C. LI
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Publication number: 20190221345Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.Type: ApplicationFiled: January 12, 2018Publication date: July 18, 2019Applicant: Intel CorporationInventors: Sai Vadlamani, Prithwish Chatterjee, Rahul Jain, Kyu Oh Lee, Sheng C. Li, Andrew J. Brown, Lauren A. Link
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Publication number: 20190206780Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Applicant: Intel CorporationInventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li