Abstract: A method for avoiding inter-modulation distortion in a communications apparatus capable of supporting carrier aggregation and communicating with a peer communications apparatus in a wireless network via at least a first CC and a second CC includes: determining a frequency adjustment value for adjusting a first oscillating frequency of a first local oscillation signal utilized for processing an RF signal of the first CC or a second oscillating frequency of a second LO signal utilized for processing an RF signal of the second CC when an RF signal or a baseband signal of the second CC is interfered with by an inter-modulation distortion signal contributed by any signal component related to the first CC; and adjusting the first oscillating frequency or the second oscillating frequency according to the frequency adjustment value.

Abstract: A wireless communication device includes a first wireless communication system and a second wireless communication system. Regarding the first wireless communication system, an up-conversion circuit up-converts a first transmit (TX) signal in a baseband to generate a second TX signal with a first carrier frequency, and a front-end circuit transmits the second TX signal to another wireless communication device. Regarding the second wireless communication system, a first down-conversion circuit down-converts a first receive (RX) signal with a second carrier frequency to generate a second RX signal with a third carrier frequency, and a second down-conversion circuit down-converts the second RX signal with the third carrier frequency to generate a third RX signal in the baseband. The third carrier frequency is different from all fundamental frequencies included in a band combination that is employed at the first wireless communication system and is supported by another wireless communication device.

Abstract: According to at least one aspect, a communication system is provided. The communication system includes a first switch device configured to receive a first plurality of radio frequency (RF) signals detected by an antenna array and provide an RF signal selected from among the first plurality of RF signals to a receiver circuit, the first plurality of RF signals comprising a first RF signal in a first frequency range and a second RF signal in a second frequency range that is different from the first frequency range; and a second switch device configured to receive a second plurality of RF signals detected by the antenna array and provide an RF signal selected from among the second plurality of RF signals to the receiver circuit, the second plurality of RF signals comprising a third RF signal in the first frequency range and a fourth RF signal in the second frequency range.

Abstract: A wireless communication device includes a first wireless communication system and a second wireless communication system. Regarding the first wireless communication system, an up-conversion circuit up-converts a first transmit (TX) signal in a baseband to generate a second TX signal with a first carrier frequency, and a front-end circuit transmits the second TX signal to another wireless communication device. Regarding the second wireless communication system, a first down-conversion circuit down-converts a first receive (RX) signal with a second carrier frequency to generate a second RX signal with a third carrier frequency, and a second down-conversion circuit down-converts the second RX signal with the third carrier frequency to generate a third RX signal in the baseband. The third carrier frequency is different from all fundamental frequencies included in a band combination that is employed at the first wireless communication system and is supported by another wireless communication device.

Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

Abstract: A method for avoiding inter-modulation distortion in a communications apparatus capable of supporting carrier aggregation and communicating with a peer communications apparatus in a wireless network via at least a first CC and a second CC includes: determining a frequency adjustment value for adjusting a first oscillating frequency of a first local oscillation signal utilized for processing an RF signal of the first CC or a second oscillating frequency of a second LO signal utilized for processing an RF signal of the second CC when an RF signal or a baseband signal of the second CC is interfered with by an inter-modulation distortion signal contributed by any signal component related to the first CC; and adjusting the first oscillating frequency or the second oscillating frequency according to the frequency adjustment value.

Abstract: A method for avoiding inter-modulation distortion in a communications apparatus capable of supporting carrier aggregation and communicating with a peer communications apparatus in a wireless network via at least a first CC and a second CC includes: determining a frequency adjustment value for adjusting a first oscillating frequency of a first local oscillation signal utilized for processing an RF signal of the first CC or a second oscillating frequency of a second LO signal utilized for processing an RF signal of the second CC when an RF signal or a baseband signal of the second CC is interfered with by an inter-modulation distortion signal contributed by any signal component related to the first CC; and adjusting the first oscillating frequency or the second oscillating frequency according to the frequency adjustment value.

Abstract: According to at least one aspect, a communication system is provided. The communication system includes a first switch device configured to receive a first plurality of radio frequency (RF) signals detected by an antenna array and provide an RF signal selected from among the first plurality of RF signals to a receiver circuit, the first plurality of RF signals comprising a first RF signal in a first frequency range and a second RF signal in a second frequency range that is different from the first frequency range; and a second switch device configured to receive a second plurality of RF signals detected by the antenna array and provide an RF signal selected from among the second plurality of RF signals to the receiver circuit, the second plurality of RF signals comprising a third RF signal in the first frequency range and a fourth RF signal in the second frequency range.

Abstract: A method for avoiding inter-modulation distortion in a communications apparatus capable of supporting carrier aggregation and communicating with a peer communications apparatus in a wireless network via at least a first CC and a second CC includes: determining a frequency adjustment value for adjusting a first oscillating frequency of a first local oscillation signal utilized for processing an RF signal of the first CC or a second oscillating frequency of a second LO signal utilized for processing an RF signal of the second CC when an RF signal or a baseband signal of the second CC is interfered with by an inter-modulation distortion signal contributed by any signal component related to the first CC; and adjusting the first oscillating frequency or the second oscillating frequency according to the frequency adjustment value.

Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

Abstract: A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer.

Abstract: A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer.

Abstract: An integer frequency divider capable of achieving a 50% duty cycle includes a source clock input end that provides a source clock, and two or more latches connected in series according to a connection order. Each of the latches includes: a signal input stage, configured to receive an input signal; a clock receiving stage, configured to treat the source clock as an input clock and an inverted clock of the source clock as an inverted signal of the input clock when the latch corresponds to an odd number in the connection order, and to treat the inverted clock as the input clock and the source clock as the inverted signal of the input clock when the latch corresponds to an even number in the connection order; and a signal output stage, configured to output an output signal according to the input signal and the source clock.

Abstract: A frequency dividing system, which comprises a control circuit, a first multiple input sharing input level triggering device, a first input level triggering group and a second input level triggering group. The first multiple input sharing input level triggering device receives a first frequency dividing signal to generate a feedback signal according to a level of a first clock signal, or receives a second frequency dividing signal to generate the feedback signal according to a level of a second clock signal. The first/second input level triggering group generates the first/second frequency dividing signal to the first multiple input sharing input level triggering device according to the feedback signal if active; and outputs a fixed voltage to the first multiple input sharing input level triggering device if non-active.

Abstract: A frequency dividing system, which comprises a control circuit, a first multiple input sharing input level triggering device, a first input level triggering group and a second input level triggering group. The first multiple input sharing input level triggering device receives a first frequency dividing signal to generate a feedback signal according to a level of a first clock signal, or receives a second frequency dividing signal to generate the feedback signal according to a level of a second clock signal. The first/second input level triggering group generates the first/second frequency dividing signal to the first multiple input sharing input level triggering device according to the feedback signal if active; and outputs a fixed voltage to the first multiple input sharing input level triggering device if non-active.

Abstract: An integer frequency divider capable of achieving a 50% duty cycle includes a source clock input end that provides a source clock, and two or more latches connected in series according to a connection order. Each of the latches includes: a signal input stage, configured to receive an input signal; a clock receiving stage, configured to treat the source clock as an input clock and an inverted clock of the source clock as an inverted signal of the input clock when the latch corresponds to an odd number in the connection order, and to treat the inverted clock as the input clock and the source clock as the inverted signal of the input clock when the latch corresponds to an even number in the connection order; and a signal output stage, configured to output an output signal according to the input signal and the source clock.

Abstract: An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency.

Abstract: A power amplifying apparatus is provided. A reference signal generator provides a reference signal having an enabling state and a disabling state. A digital power amplifier generates a current based on the reference signal and an input signal. An output signal of the digital power amplifier is related to the current. When the reference signal is in the enabling state, the current is related to the input signal. When the reference signal is in the disabling state, the current is irrelevant to the input signal. During the enabling state of the reference signal, a data generator provides an output alternating between an in-phase signal and a quadrature-phase signal as the input signal to the digital power amplifier. When the reference signal is in the disabling state, the data generator provides a fixed signal as the input signal to the digital power amplifier.

Abstract: A direct-conversion transmitter including an oscillator, a frequency divider, a transmitter, and a filter is provided. The oscillator generates an oscillating signal with an original frequency. The frequency divider performs frequency dividing on the oscillating signal, so as to generate a carrier signal. The transmitter receives the carrier signal from the frequency divider and generates an output signal based on the carrier signal and a data signal. The filter is coupled between the frequency divider and the transmitter. The filter filters out an interference signal fed-back from the transmitter to the oscillator, wherein the interference signal may cause the oscillating signal to float.

Abstract: A power amplifying apparatus is provided. A reference signal generator provides a reference signal having an enabling state and a disabling state. A digital power amplifier generates a current based on the reference signal and an input signal. An output signal of the digital power amplifier is related to the current. When the reference signal is in the enabling state, the current is related to the input signal. When the reference signal is in the disabling state, the current is irrelevant to the input signal. During the enabling state of the reference signal, a data generator provides an output alternating between an in-phase signal and a quadrature-phase signal as the input signal to the digital power amplifier. When the reference signal is in the disabling state, the data generator provides a fixed signal as the input signal to the digital power amplifier.