Patents by Inventor Sheng-Chin Kung
Sheng-Chin Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848369Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.Type: GrantFiled: February 16, 2022Date of Patent: December 19, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
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Patent number: 11456178Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.Type: GrantFiled: June 15, 2021Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes F. Swenberg
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Publication number: 20220173220Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
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Patent number: 11282936Abstract: Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.Type: GrantFiled: September 14, 2020Date of Patent: March 22, 2022Assignee: Applied Materials, Inc.Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
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Patent number: 11271097Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.Type: GrantFiled: October 26, 2020Date of Patent: March 8, 2022Assignee: Applied Materials, Inc.Inventors: Steven C. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes Swenberg
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Publication number: 20210398814Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.Type: ApplicationFiled: June 15, 2021Publication date: December 23, 2021Applicant: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes F. Swenberg
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Patent number: 11011635Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.Type: GrantFiled: December 12, 2017Date of Patent: May 18, 2021Assignee: Applied Materials, Inc.Inventors: Sheng-Chin Kung, Hua Chung
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Publication number: 20210134986Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.Type: ApplicationFiled: October 26, 2020Publication date: May 6, 2021Applicant: Applied Materials, Inc.Inventors: Steven C. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes Swenberg
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Publication number: 20200411656Abstract: Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
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Patent number: 10861722Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.Type: GrantFiled: September 23, 2019Date of Patent: December 8, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Benjamin Colombeau, Sheng-Chin Kung, Patricia M. Liu
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Patent number: 10777650Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.Type: GrantFiled: April 24, 2017Date of Patent: September 15, 2020Assignee: Applied Materials, Inc.Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
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Publication number: 20200152493Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.Type: ApplicationFiled: September 23, 2019Publication date: May 14, 2020Inventors: Benjamin COLOMBEAU, Sheng-Chin KUNG, Patricia M. LIU
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Publication number: 20200144397Abstract: Methods and apparatuses for processing substrates, such as during silicon-germanium pre-cleans, are provided. A method includes introducing the substrate into a processing system, where the substrate contains a plurality of silicon-containing (e.g., SiGe) fins and a contaminant disposed on the silicon-containing fins, and exposing the substrate to a plasma treatment to remove at least a portion of the contaminant disposed from the silicon-containing fins. The method also includes exposing the substrate to an oxidation treatment to produce an oxide layer on the silicon-containing fins and the remaining contaminant thereon, then exposing the substrate to a dry-clean treatment to remove the oxide layer and the remaining contaminant from the silicon-containing fins and produce a cleaned surface thereon, and depositing an epitaxial layer on the cleaned surface on the silicon-containing fins.Type: ApplicationFiled: September 17, 2019Publication date: May 7, 2020Applicants: Applied Materials, Inc., Applied Materials, Inc.Inventors: Abhishek DUBE, Sheng-Chin KUNG, Malcolm BEVAN, Johanes SWENBERG
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Patent number: 10249479Abstract: Embodiments described herein generally relate to plasma process apparatus. In one embodiment, the plasma process apparatus includes a plasma source assembly. The plasma source assembly may include a first coil, a second coil surrounding the first coil, and a magnetic device disposed outside the first and inside the second coil. The magnet enables additional tuning which improves uniformity control of the processes on the substrate.Type: GrantFiled: December 31, 2015Date of Patent: April 2, 2019Assignee: Applied Materials, Inc.Inventors: Joseph F. Aubuchon, Tza-Jing Gung, Travis Lee Koh, Nattaworn Boss Nunta, Sheng-Chin Kung, Steven Lane, Kartik Ramaswamy, Yang Yang
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Publication number: 20180166570Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.Type: ApplicationFiled: December 12, 2017Publication date: June 14, 2018Inventors: Sheng-Chin KUNG, Hua CHUNG
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Patent number: 9966438Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.Type: GrantFiled: January 27, 2017Date of Patent: May 8, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Yi-Chiau Huang, Hua Chung, Sheng-Chin Kung, Xuebin Li
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Publication number: 20180083104Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.Type: ApplicationFiled: January 27, 2017Publication date: March 22, 2018Inventors: Yi-Chiau HUANG, Hua CHUNG, Sheng-Chin KUNG, Xuebin LI
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Publication number: 20170309719Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.Type: ApplicationFiled: April 24, 2017Publication date: October 26, 2017Inventors: Shiyu SUN, Nam Sung KIM, Bingxi Sun WOOD, Naomi YOSHIDA, Sheng-Chin KUNG, Miao JIN
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Publication number: 20160225590Abstract: Embodiments described herein generally relate to plasma process apparatus. In one embodiment, the plasma process apparatus includes a plasma source assembly. The plasma source assembly may include a first coil, a second coil surrounding the first coil, and a magnetic device disposed outside the first and inside the second coil. The magnet enables additional tuning which improves uniformity control of the processes on the substrate.Type: ApplicationFiled: December 31, 2015Publication date: August 4, 2016Inventors: Joseph F. Aubuchon, Tza-Jing Gung, Travis Lee Koh, Nattaworn Nuntaworanuch, Sheng-Chin Kung, Steven Lane, Kartik Ramaswamy, Yang Yang
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Publication number: 20040109813Abstract: An art is provided to realize a current emitting device capable of emitting current of higher density under the same or lower onset emission voltage. The current emitting device is preferably an array of carbon nanotubes or a film including carbon nanotubes. The art is based on oxidizing a current emitting device composed of material including carbon, until the current emitting device has at least part thereof changed in shape. The current emitting device thus processed works better with a display, or becomes capable of emitting current of higher density under the same or lower onset emission voltage. As far as experiments showed, the emitted current density achieved by the art can be eight times the amount emitted by an array of nanotubes having not been processed according to the art, and the onset emission voltage can be lowered by the art from 0.8 V/&mgr;m to 0.5 V/&mgr;m.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Applicant: National Tsing Hua UniversityInventors: Kuo-Chu Hwang, Sheng-Chin Kung