Patents by Inventor Sheng Hsiang Chang
Sheng Hsiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194805Abstract: The present invention provides a photodiode structure, which includes a chip, an electrode group, an electrode protection layer and a metal alloy band-pass optical film. The electrode group is arranged on the chip, and the electrode group includes a positive electrode and a negative electrode; the electrode protection layer is arranged on the chip and covers the electrode group; the metal alloy band-pass optical film is arranged on the electrode protection layer and includes a plurality of layered structures, and the plurality of layered structures includes at least two metal alloy material layers.Type: ApplicationFiled: December 5, 2023Publication date: June 13, 2024Inventors: Yen-Hsiang CHANG, Sheng-Wei CHEN
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Patent number: 11983475Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.Type: GrantFiled: February 7, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Publication number: 20240086612Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
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Publication number: 20220408054Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.Type: ApplicationFiled: August 21, 2022Publication date: December 22, 2022Applicant: MEDIATEK INC.Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
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Patent number: 11457173Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.Type: GrantFiled: January 21, 2021Date of Patent: September 27, 2022Assignee: MEDIATEK INC.Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
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Publication number: 20210280148Abstract: The present invention provides a processor including a source generator, a request synchronization signal generator and an output circuit. The source generator is configured to generate image data of a frame. The request synchronization signal generator is configured to generate a request synchronization signal to an integrated circuit only after the source generator generates the image data of the frame completely, wherein the request synchronization signal is used to trigger the integrated circuit to send a synchronization signal to the processor. The output circuit is configured to send the image data of the frame to the integrated circuit only after receiving the synchronization signal generated from the integrated circuit in response to the request synchronization signal.Type: ApplicationFiled: February 24, 2021Publication date: September 9, 2021Inventors: Chang-Chu Liu, Sheng-Hsiang Chang, Kang-Yi Fan, You-Min Yeh
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Publication number: 20210266495Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.Type: ApplicationFiled: January 21, 2021Publication date: August 26, 2021Inventors: Kang-Yi Fan, Chin-Wen Liang, Chang-Chu Liu, Sheng-Hsiang Chang, You-Min Yeh
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Patent number: 10636718Abstract: A packaging module includes a substrate, a chip firmly mounted on the substrate, a frame firmly connected to the substrate via a gold-to-gold bonding and a cover firmly connected to the frame via the same gold-to-gold bonding. With the inorganic bonding structure, the packaging module is able to endure high temperature and high pressure without the worry of bonding agent being damaged by environmental condition change.Type: GrantFiled: September 21, 2018Date of Patent: April 28, 2020Assignee: Chang Sheng Hsiang ChangInventor: Sheng Hsiang Chang
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Publication number: 20190088567Abstract: A packaging module includes a substrate, a chip firmly mounted on the substrate, a frame firmly connected to the substrate via a gold-to-gold bonding and a cover firmly connected to the frame via the same gold-to-gold bonding. With the inorganic bonding structure, the packaging module is able to endure high temperature and high pressure without the worry of bonding agent being damaged by environmental condition change.Type: ApplicationFiled: September 21, 2018Publication date: March 21, 2019Inventor: Sheng Hsiang Chang