Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A process for producing a barrier composition includes subjecting a siloxane compound having 1 to 3 amino groups and an aqueous solution including water and an alcohol to hydrolysis and first-stage condensation under required conditions, subjecting a first colloidal mixture obtained and an additional alcohol to second-stage condensation, subjecting a second colloidal mixture obtained, which has a particular solid content, to heating under required conditions, and subjecting a cured product obtained to aging under required conditions. A barrier composition produced by the process is also disclosed.

Abstract: A voltage identification definition (VID) reference voltage generation circuit and a boot voltage generating method thereof are provided. In the boot voltage generating method, a VID reference voltage generation circuit is provided. The VID reference voltage generation circuit includes a preset voltage providing unit, a switch and a VID input signal detection unit. When the VID input signal detection unit detects no input of a VID signal, a control signal is generated to control the switch, such that the preset voltage providing unit provides an adjustable preset voltage.

Abstract: An integrated circuit with multi-functional parameter setting and a multi-functional parameter setting method of the integrated circuit are provided. The multi-functional parameter setting method includes following steps: providing the integrated circuit which includes a switch unit and a multi-functional pin that is coupled to an external setting unit, sensing a programmable reference voltage of the external setting unit through one operation of the switch unit and executing a first function setting according to the programmable reference voltage, and sensing a programmable reference current of the external setting unit through another operation of the switch unit and executing a second function setting according to the programmable reference current.

Abstract: An integrated circuit with multi-functional parameter setting and a multi-functional parameter setting method of the integrated circuit are provided. The multi-functional parameter setting method includes following steps: providing the integrated circuit which includes a switch unit and a multi-functional pin that is coupled to an external setting unit, sensing a programmable reference voltage of the external setting unit through one operation of the switch unit and executing a first function setting according to the programmable reference voltage, and sensing a programmable reference current of the external setting unit through another operation of the switch unit and executing a second function setting according to the programmable reference current.

Abstract: A voltage identification definition (VID) reference voltage generation circuit and a boot voltage generating method thereof are provided. In the boot voltage generating method, a VID reference voltage generation circuit is provided. The VID reference voltage generation circuit includes a preset voltage providing unit, a switch and a VID input signal detection unit. When the VID input signal detection unit detects no input of a VID signal, a control signal is generated to control the switch, such that the preset voltage providing unit provides an adjustable preset voltage.

Abstract: A method for Wear-Leveling includes: utilizing a comparison circuit to compare an average erase count with an erase count of a first data block; and utilizing a first free block as a replacement for storing data content of the first data block so as to make the first data block become a free block when the erase count of the first data block is smaller than the average erase count.

Abstract: A storage apparatus includes a first storage unit and at least a second storage unit. A method for accessing the storage apparatus generates a plurality of bad block lists regarding the plurality of the storage units, respectively, and according to at least one bad block indicated by a bad block list of the first storage unit, configures at least a good block in each second storage unit corresponding to the at least one bad block of the first storage unit as a replacement block of each second storage unit. Accordingly, the method generates a mapping result of each second storage unit according to a bad block list of the second storage unit and each replacement block, and accesses the storage apparatus according to the bad block list of the first storage unit and each mapping result.