Abstract: A device includes an integrated circuit die attached to a substrate; a lid attached to the integrated circuit die; a sealant on the lid; a spacer structure attached to the substrate adjacent the integrated circuit die; and a cooling cover attached to the spacer structure, wherein the cooling cover extends over the lid, wherein the cooling cover attached to the lid by the sealant. In an embodiment, the device includes a ring structure on the substrate, wherein the ring structure is between the spacer structure and the integrated circuit die.

Abstract: A capacitive ultrasonic transducer device includes a substrate, a first capacitive structure, a second capacitive structure, a first film structure and a second film structure. The first capacitive structure is disposed on the substrate, and includes a first electrode and a second electrode. A first gap and a dielectric layer are located between the first electrode and the second electrode. The second capacitive structure is disposed on the substrate, and includes a third electrode and a fourth electrode. A second gap is located between the third electrode and the fourth electrode. The first film structure is configured to seal the first gap. The second film structure is connected to the third electrode and the fourth electrode, and configured to seal the second gap. A first width between the first electrode and the second electrode is different from a second width of the second gap.

Abstract: Disclosed is a power storage device and method for discharging the same, which configures the power storage device to perform an electric power output under a discharging limit upon coupling with a load device and before any authentication is conducted. The discharging limit for the electric power output will be lifted only when an authentication result between the power storage device and the load device indicates a successful authentication.

Abstract: Active cables and communication methods can provide data path redundancy with power sharing. In one illustrative cable implementation, the cable includes a first connector with contacts to supply power to circuitry in the first connector; a second connector with contacts to supply power to a component of the circuitry in the first connector via a first connection that prevents reverse current flow; and a third connector with contacts to supply power to the same component via a second connection that prevents reverse current flow. An illustrative method implementation includes: using contacts of a first connector to supply power to circuitry in the first connector; and using contacts in each of multiple redundant connectors to supply power to a component of said circuitry in the first connector via a corresponding diodic or switched connection that prevents reverse current flow.

Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.

Abstract: The present invention relates to a composition comprising an amino acid-modified polymer, a carboxypolysaccharide, and may further include a metal ion for anti-adhesion and vector application. More specifically, the invention relates to a thermosensitive composition having enhanced mechanical and improved water-erosion resistant properties for efficiently preventing tissue adhesions and can serve as a vector with bio-compatible, bio-degradable/absorbable, and in-vivo sustainable properties.

Abstract: An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.

Abstract: Synthetic amino acid-modified polymers and methods of making the same and using the same are disclosed. The synthetic amino acid-modified polymers possess distinct thermosensitive, improved water-erosion resistant, and enhanced mechanical properties, and are suitable of reducing or preventing formation of postoperative tissue adhesions. Additionally, the amino acid-modified polymers can also be used as a vector to deliver pharmaceutically active agents.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: A constraining apparatus and a constraining device are described. The constraining apparatus includes a base, a positioning assembly, and a cushion assembly. The positioning assembly includes a plurality of positioning members arranged in sequence and located between two end plate assemblies. The cushion assembly is disposed on at least one of two sides of the positioning member that are opposite each other in the first direction. The constraining apparatus includes a first state and a second state, where in the first state, adjacent two of the positioning members abut against each other, such that an accommodating space for accommodating a battery cell is formed between the adjacent two of the positioning members, and the cushion assembly is configured to abut against the battery cell and the positioning members. In the second state, the plurality of positioning members are spaced apart from each other in the first direction.

Abstract: A thermal module includes a radiating fin unit having a plurality of superposed radiating fin assemblies, and a plurality of groups of heat pipes. The heat pipes respectively have a heat absorbing section and a heat dissipating section formed at two opposite ends thereof. The heat absorbing sections in each heat pipe group is in contact with a heat source, and the heat dissipating sections in the same heat pipe group is sandwiched between two adjacent ones of the radiating fin assemblies. The thermal module is characterized in that the heat dissipating sections are horizontally extended through the radiating fin assemblies from one of two opposite shorter sides to another shorter side along two parallel longer sides thereof, such that the heat dissipating sections not only have a maximum contact area with the radiating fin assemblies, but also give the radiating fin unit an enhanced structural strength.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.

Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.

Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.