Abstract: A semiconductor device is provided. The semiconductor device includes a first field effect transistor (FET) region, a second FET region and a backside signal distribution network (BSSDN). The first FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends through the STI and the ILD. The second FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends to the STI. The BSSDN is disposed on the ILD in the first and second regions to contact with the contact in the first FET region.

Abstract: A method of fabrication a semiconductor device includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.

Abstract: A semiconductor device includes a shallow trench isolation region extending from a first end surface to a second end surface. The semiconductor device further includes an inner layer dielectric region extending from a third end surface to a fourth end surface. The inner layer dielectric region is arranged such that the fourth end surface is in direct contact with the first end surface. The semiconductor device further includes a transistor arranged in the inner layer dielectric region and a contact via electrically connecting the transistor to a buried power rail. The contact via extends from the second end surface to the third end surface and is narrower at the fourth end surface than at the first end surface.

Abstract: A stacked field effect transistor (stacked-FET) device includes a first layer comprising at least one first layer transistor structure comprising a plurality of first layer terminals, a diffusion break dielectric fill region adjacent to one of the first layer terminals, a second layer overlying and adjacent to the first layer and comprising at least one second layer transistor structure comprising a plurality of second layer terminals, and a contact wiring between the first layer and the second layer passing through the diffusion break dielectric fill region of the first layer and connecting with one of the second layer terminals.

Abstract: A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Abstract: Example implementations described herein include a laser source and associated methods of operation that can balance or reduce uneven beam profile problem and even improve plasma heating efficiency to enhance conversion efficiency and intensity for extreme ultraviolet radiation generation. The laser source described herein generates an auxiliary laser beam to augment a pre-pulse laser beam and/or a main-pulse laser beam, such that uneven beam profiles may be corrected and/or compensated. This may improve an intensity of the laser source and also improve an energy distribution from the laser source to a droplet of a target material, effective to increase an overall operating efficiency of the laser source.

Abstract: A semiconductor structure includes a backside power rail disposed in a backside dielectric layer, and dielectric spacer layers laterally extending inwardly from opposing sidewalls of the backside dielectric layer and on a portion of a bottom surface of the backside power rail.

Abstract: A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Abstract: A semiconductor device includes a transistor having a source/drain region and a contact disposed on the source/drain region. The semiconductor device further includes a via extending from the contact along a side of the source/drain region to a power element. The contact and the via each comprise a plurality of conductive materials.

Abstract: A semiconductor device that includes a stack of sheet semiconductor layers, and source and drain regions positioned on opposing sides of a channel region in the stack of sheet semiconductor layers. A first contact is present to an upper sheet portion of the source and drain regions for the stack of sheet semiconductor layers. An extended epitaxial semiconductor region is present in contact with the lower sheet portion of the source/drain regions for the stack of sheet semiconductor layers. A second contact is present in direct contact with an upper surface of the extended epitaxial semiconductor region. A notch may be present in the upper surface of the extended semiconductor region to increase contact surface to the second contact.

Abstract: A radiation source apparatus includes a vessel, a laser source, a collector, a horizontal obscuration bar, and a reflective mirror. The vessel has an exit aperture. The laser source is configured to emit a laser beam to excite a target material to form a plasma. The collector is disposed in the vessel and configured to collect a radiation emitted by the plasma and to reflect the collected radiation to the exit aperture of the vessel. The horizontal obscuration bar extends from a sidewall of the vessel at least to a position between the laser source and the exit aperture of the vessel. The reflective mirror is in the vessel and connected to the horizontal obscuration bar.

Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system including a radiation source and an EUV control system integrated with the radiation source. The EUV control system includes a 3-dimensional diagnostic module (3DDM) designed to collect a laser beam profile of a laser beam from the radiation source in a 3-dimensional (3D) mode, an analysis module designed to analyze the laser beam profile, a database designed to store the laser beam profile, and an EUV control module designed to adjust the radiation source. The analysis module is coupled with the database and the EUV control module. The database is coupled with the 3DDM and the analysis module. The EUV control module is coupled with the analysis module and the radiation source.

Abstract: A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.

Abstract: A semiconductor device includes a wafer having at least two source/drain (S/D) epi regions. A power rail is arranged on a backside of the wafer. A backside contact (BSCA) has a first portion including a backside local interconnect configured to connect the S/D epi regions together. A plurality of frontside signal wires are connected to the backside local interconnect through a first front side contact.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.

Abstract: A semiconductor device comprising a contact comprising a first section and a second section; wherein the first section of the contact is located on a front side of a source or drain; wherein the second section extends from the front side of the source or drain to a backside of the source or drain; wherein the second section of the contact is comprised of a via and a connection area; wherein the via has a first width and the connection area has a second width, and wherein the second width is larger than the first width.

Abstract: A microelectronic structure including a first nano device, where the first nano device includes a plurality of transistors. A bottom dielectric isolation located on the backside of each of the plurality of transistors of the first nano device. A separating dielectric layer located on the backside of the bottom dielectric isolation layer, where the separating dielectric layer is a continuous layer on the backside of each of the plurality of transistors of the first nano device.

Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.

Abstract: Backside contacts wrapping around source/drain regions provide increased contact areas for electrical connections between field-effect transistors and metallization layers. Cavities formed within a device layer expose sidewalls of selected source/drain regions. The backside contacts extend within such cavities and adjoin the sidewall surfaces and bottom surfaces of the selected source/drain regions.