Patents by Inventor Sheng-Ming Wu
Sheng-Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162051Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.Type: ApplicationFiled: April 27, 2023Publication date: May 16, 2024Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Patent number: 11984431Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.Type: GrantFiled: January 19, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Ming Wu, Yung-Lung Lin, Zhi-Yang Wang, Sheng-Chau Chen, Cheng-Hsien Chou
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Patent number: 11968556Abstract: A network quality measurement method and system are provided. In the method, a movement path and a movement speed of a vehicle device are determined according to a size of a space and an endurance time of the vehicle device, and the vehicle device is controlled to move on the movement path at the movement speed. During a movement of the vehicle device, a network quality in the space is measured according to a measurement frequency to generate network quality data. Whether the network quality in the space is changed is determined according to the network quality data. Whether there is an obstacle around the vehicle device is detected. When it is determined that the network quality in the space is changed or the obstacle is detected around the vehicle device, at least one of the movement path, the movement speed, and the measurement frequency is adjusted.Type: GrantFiled: December 26, 2021Date of Patent: April 23, 2024Assignee: Industrial Technology Research InstituteInventors: Hui-Ping Kuo, Sheng-Chieh Huang, Hsin-Hui Hwang, Yi-Ming Wu, Man Ju Chien
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Patent number: 11951569Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.Type: GrantFiled: May 12, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
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Publication number: 20240090230Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.Type: ApplicationFiled: January 9, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20240084455Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.Type: ApplicationFiled: February 8, 2023Publication date: March 14, 2024Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
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Publication number: 20240079268Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
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Publication number: 20140097540Abstract: A semiconductor structure includes a silicon substrate, a titanium layer, a nickel layer, a silver layer and a metallic adhesion layer, wherein the silicon substrate comprises a back surface, and the titanium layer comprises an upper surface. The titanium layer is formed on the back surface, the nickel layer is formed on the upper surface, the silver layer is formed on the nickel layer, and the metallic adhesion layer is formed between the nickel layer and the silver layer.Type: ApplicationFiled: November 15, 2012Publication date: April 10, 2014Applicant: CHIPBOND TECHNOLOGY CORPORATIONInventors: Hsiang-Chin Chiu, Sheng-Ming Wu, Kuang-Hao Yang, Kung-An Lin, Chen-Yu Wang
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Publication number: 20030048175Abstract: This invention represents a portable biometric verification and storage device. The portable device performs the biometric characteristics recognition or verification for providing high security of personal identification by collating digital Biometric Identification Record (BIR) stored in the device and personal activated biometric characteristics. The Biometric Identification Record (BIR) includes a memory for storing at least one or more personal biometric characteristics database and for storing at least one or more ID of each person and personal information in a portable biometric verification and storage device.Type: ApplicationFiled: September 7, 2001Publication date: March 13, 2003Inventors: Po-Tong Wang, Sheng-Ming Wu
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Publication number: 20030048904Abstract: This invention represents a Web-based biometric authorization apparatus. The present invention relates to live biometric characteristics which are captured by a biometric capture device and, in particular, to the Biometric Identification Record (BIR) and personal information which are stored in a digitized data storage apparatus. It is therefore an object of the present invention to provide the further data process which includes compression and decompression function, encryption and decryption function, and to provide the BIR process which relates to calculation, collation and verification as a secured mechanism. The apparatus is operatively coupled to a remote site so as to establish an Internet communication link through wired or wireless communications. Therefore, the biometric verification is performed with peripheral devices such as POS terminals, ATM terminals, credit card reader, access control or other control mechanism.Type: ApplicationFiled: September 7, 2001Publication date: March 13, 2003Inventors: Po-Tong Wang, Sheng-Ming Wu
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Publication number: 20020163421Abstract: This invention represents a method of bank card and credit card with fingerprint authentication for identifying whether a user is a registered owner of the card. The reference fingerprint data will be digitized and stored in an IC chip or stored on a magnetic strip of a bank card and a credit card. Therefore, this invention can identify the correct user of the bank card or the credit card by collating the measured fingerprint data with the reference fingerprint data via a fingerprint ATM terminal or a fingerprint reading device of the credit card. It could prevent the illegal use of these cards and heavy financial problems of issuing banks.Type: ApplicationFiled: May 7, 2001Publication date: November 7, 2002Inventors: Po-Tong Wang, Sheng-Ming Wu