Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

Abstract: A display substrate, a display apparatus and a manufacturing method are provided. The display substrate includes: a base substrate; a first electrode layer on a side of the base substrate; a light-emitting layer on a side of the first electrode layer facing away from the base substrate including a plurality of light-emitting portions; a second electrode layer on a side of the light-emitting layer facing away from the first electrode layer; a first transparent inhibitor layer including a plurality of mutually separated first pattern portions; and an auxiliary electrode layer including an auxiliary electrode pattern formed by inhibition of the first pattern portions, where at least part of an orthographic projection of the auxiliary electrode pattern on the base substrate is separated from orthographic projections of the first pattern portions on the base substrate, and the auxiliary electrode pattern is in contact and electrically connected with the second electrode layer.

Abstract: Systems and methods for deep neural network (DNN)-based cross component prediction are provided. A method includes inputting a reconstructed luma block of an image or video into a DNN; and predicting, by the DNN, a reconstructed chroma block of the image or video based on the reconstructed luma block that is input. Luma and chroma reference information and side information may also be input into the DNN to predict the reconstructed chroma block. The various inputs may also be generated using processes such as downsampling and transformation.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Abstract: The present invention discloses a shed tunnel structure for preventing a falling rock, including a shed tunnel body and a buffer plate for bearing impact of the falling rock, where the shed tunnel body includes a first supporting structure, and the first supporting structure is arranged on a side away from a ramp; one end of the buffer plate is connected to the ramp; a side face of the buffer plate close to the shed tunnel body is in movable contact with the first supporting structure, and the contact position is close to the other end of the buffer plate. The objective of resisting continuous impact of the falling rock can be achieved through the structural design.

Abstract: A power supply suppression circuit (10), a chip and a communication terminal that only achieve the enhancement of the power supply suppression capability from an AC, without generating additional circuit power consumption. The power supply suppression circuit (10) comprises a sampling unit (105), a compensation unit (106), and an amplification unit (107). The sampling unit (105) is connected to the compensation unit (106), and the compensation unit (106) is connected to the amplification unit (107). The power supply suppression circuit (10) obtains an AC signal from a preset sampling node position of a low dropout regulator, and generates an enhancement signal in phase with the AC signal on a power supply (Vdd) on the basis of the AC signal, such that the input end voltage of the power output stage of the low dropout regulator immediately follows the voltage change of the power supply (Vdd).

Abstract: A notched filter includes a multilayer having alternating first and second polymer layers, the first polymer layers each including an isotropic polymer thin film having in-plane refractive indices n1x and n1y, and the second polymer layers each including an isotropic or anisotropic polymer thin film having in-plane refractive indices n2x and n2y, where a thickness of each successive first polymer layer decreases with increasing distance from a centerline of the multilayer, and a thickness of each successive second polymer layer increases with increasing distance from the centerline. Such a filter may be configured to reflect incident light having a desired polarization state within a predetermined and relatively narrow band.

Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.

Abstract: An image sensor structure including a substrate, a first pixel structure, a second pixel structure, a dielectric layer, and a conductive layer stack is provided. The first pixel structure includes a first light sensing device. The second pixel structure includes a second light sensing device. The conductive layer stack includes conductive layers. The conductive layer stack has a first opening and a second opening. The first opening is located directly above the first light sensing device and passes through the conductive layers. The second opening is located directly above the second light sensing device and passes through the conductive layers. The second minimum width of the second opening is smaller than the first minimum width of the first opening. The luminous flux of the second pixel structure is different from the luminous flux of the first pixel structure.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: Embodiments of this application provide a peer-to-peer network transmission method, applied to a first peer node in the peer-to-peer network. The transmission method includes obtaining a target public network IP address and a target public network port of a second peer node from a networking service center, wherein the second peer node is located in the peer-to-peer network and configured to access a public network through a corresponding NAT device, and wherein public network IP addresses and public network ports of all nodes in the peer-to-peer network are collected by the networking service center in advance; and establishing a connection with the second peer node based on the target public network IP address and the target public network port to perform NAT traversal transmission.

Abstract: A system for visualization and quantification of ultrasound imaging data according to embodiments of the present disclosure may include a display unit, and a processor communicatively coupled to the display unit and to an ultrasound imaging apparatus for generating an image from ultrasound data representative of a bodily structure and fluid flowing within the bodily structure. The processor may be configured to estimate axial and lateral velocity components of the fluid flowing within the bodily structure, determine a plurality of flow directions within the image based on the axial and lateral velocity components, differentially encode the flow directions based on flow direction angle to generate a flow direction map, and cause the display unit to concurrently display the image including the bodily structure overlaid with the flow direction map.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A tape laying device includes a tape transmission mechanism, a compaction head mechanism, a cutter mechanism, a heating mechanism and a motion mechanism. The tape transmission mechanism is configured to transmit the pre-impregnated tape. The compaction head mechanism, connected with the tape transmission mechanism, is configured to depress and drive the pre-impregnated tape transmitted by the tape transmission mechanism to follow a moving path so as to adhere the pre-impregnated tape onto the mould surface. The cutter mechanism is configured to cut the pre-impregnated tape. The heating mechanism, disposed downstream to the cutter mechanism, is configured to heat the pre-impregnated tape. The motion mechanism is used to have the cutter mechanism having an active path to move toward the moving path while the cutter mechanism cuts the pre-impregnated tape.

Abstract: An image sensor structure and a method of fabricating the structure are disclosed, in image sensor structure, at least one die is bonded to pixel substrate by bonding first bonding layer to second bonding layer, and the die includes signal processing circuit and/or storage device for photosensitive elements in pixel substrate. The die is bonded to the pixel substrate so that the signal processing circuit and/or storage device is/are coupled to photosensitive elements in pixel substrate. In this way, signal processing and/or storage functions of the image sensor can be provided without additional occupation of the area of the pixel substrate, allowing for more photosensitive elements to be arranged on the pixel substrate with the same area and thus resulting in a larger photosensitive area. Moreover, less wiring is needed on the 2D plane of the pixel substrate, helping in reducing interference with signals and delays and improving imaging quality.

Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

Abstract: The present disclosure describes ultrasound systems configured to enhance flow imaging and analysis by adaptively adjusting one or more imaging parameters in response to acquired flow measurements. Example systems can include an ultrasound transducer and one or more processors. Using the system components, mean flow velocity magnitude and acceleration can be determined within a target region during an acquisition phase, which may include a cardiac cycle. One or more adjusted flow imaging parameters, such as adjusted ensemble length, temporal smoothing filter length and/or step size, can be determined based on the acquired flow measurements to increase the signal quality of newly acquired ultrasound echo signals. The adjusted flow imaging parameters can then be applied by the ultrasound transducer during a second acquisition phase.

Abstract: This disclosure provides a method, a computing system, and a computer program product for managing prefetching of pages in a database system. The method comprises obtaining shared information associated with page access, wherein the shared information associated with the page access includes information associated with the page access from a plurality of computing nodes. The method further comprises determining whether to prefetch a number of pages into a global buffer pool based at least on the shared information associated with the page access using a sequential prefetching method.

Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The display may have a number of independently controllable viewing zones. Each viewing zone displays a respective two-dimensional image. Each eye of the viewer may receive a different one of the two-dimensional images, resulting in a perceived three-dimensional image. The electronic device may include display pipeline circuitry that generates and processes content to be displayed on the lenticular display. Content generating circuitry may initially generate content that includes a plurality of two-dimensional images, each two-dimensional image corresponding to a respective viewing zone. Pre-processing circuitry may subsequently anisotropically resize each two-dimensional image. Pixel mapping circuitry may then be used to map the resized two-dimensional images to the array of pixels in the lenticular display.