Patents by Inventor Sheng-Wei YEH
Sheng-Wei YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090234Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
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Publication number: 20230072507Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Patent number: 11502050Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: GrantFiled: February 8, 2021Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Publication number: 20220336653Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: ApplicationFiled: June 23, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Publication number: 20220302060Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Inventors: Anhao CHENG, Chun-Chang LIU, Sheng-Wei YEH
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Patent number: 11411112Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: GrantFiled: May 31, 2020Date of Patent: August 9, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Patent number: 11373970Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.Type: GrantFiled: January 17, 2020Date of Patent: June 28, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Anhao Cheng, Chun-Chang Liu, Sheng-Wei Yeh
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Publication number: 20210159196Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: ApplicationFiled: February 8, 2021Publication date: May 27, 2021Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Patent number: 10916517Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: GrantFiled: December 26, 2019Date of Patent: February 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Publication number: 20210036147Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: ApplicationFiled: May 31, 2020Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Patent number: 10658315Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: GrantFiled: March 27, 2018Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Publication number: 20200152589Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.Type: ApplicationFiled: January 17, 2020Publication date: May 14, 2020Inventors: Anhao CHENG, Chun-Chang LIU, Sheng-Wei YEH
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Publication number: 20200144208Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: ApplicationFiled: December 26, 2019Publication date: May 7, 2020Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Patent number: 10541218Abstract: A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.Type: GrantFiled: January 6, 2017Date of Patent: January 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Anhao Cheng, Chun-Chang Liu, Sheng-Wei Yeh
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Publication number: 20190304939Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
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Patent number: 10354965Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.Type: GrantFiled: September 28, 2017Date of Patent: July 16, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih Wei Bih, Chun-Chih Lin, Sheng-Wei Yeh, Yen-Yu Chen, Chih-Wei Lin, Wen-Hao Cheng
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Publication number: 20190096834Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih Wei BIH, Chun-Chih LIN, Sheng-Wei YEH, Yen-Yu CHEN, Chih-Wei LIN, Wen-Hao CHENG
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Patent number: 10113228Abstract: The present disclosure provides a method for controlling a semiconductor deposition operation. The method includes (i) identifying a first target lifetime in a physical vapor deposition (PVD) system; (ii) inputting the first target lifetime into a processor; (iii) outputting, by the processor, a plurality of first operation parameters according to a plurality of compensation curves; and (iv) performing the first operation parameters in the PVD system. The first operation parameters includes, but not limited to, an RF power tuning, a DC voltage tuning, a target to chamber pedestal spacing tuning, an AC bias tuning, an impedance tuning, a reactive gas flow tuning, an inert gas flow tuning, a chamber pedestal temperature tuning, or a combination thereof.Type: GrantFiled: June 20, 2014Date of Patent: October 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Liang Cheng, Sheng-Wei Yeh, Chia-Hsi Wang, Wei-Jen Chen, Yen-Yu Chen, Chang-Sheng Lee, Wei Zhang
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Patent number: 10064286Abstract: A manufacturing method of a structure of a thin fan includes providing a plastic material containing a plurality of metal particles and forming a housing from the plastic material. A part surface of the housing is removed, and a layout area and an extended circuit are formed on the housing. One terminal of the extended circuit connects to the layout area. A first signal connecting structure is disposed on the housing. The first signal connecting structure connects to the other terminal of the extended circuit. A metal layer is disposed on the layout area and the extended circuit.Type: GrantFiled: March 4, 2016Date of Patent: August 28, 2018Assignee: DELTA ELECTRONICS, INC.Inventors: Sheng-Wei Yeh, Chiu-Kung Chen, Cheng-Chieh Liu, Shao-Chang Tu
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Publication number: 20180151525Abstract: A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.Type: ApplicationFiled: January 6, 2017Publication date: May 31, 2018Inventors: Anhao CHENG, Chun-Chang LIU, Sheng-Wei YEH