Patents by Inventor Sheng-De Liu
Sheng-De Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11233145Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.Type: GrantFiled: April 10, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sheng-De Liu, Chung-Yen Chou, Shih-Chang Liu
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Publication number: 20200243675Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: SHENG-DE LIU, CHUNG-YEN CHOU, SHIH-CHANG LIU
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Patent number: 10622471Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.Type: GrantFiled: November 26, 2018Date of Patent: April 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sheng-De Liu, Chung-Yen Chou, Shih-Chang Liu
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Patent number: 10325910Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.Type: GrantFiled: March 5, 2018Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 10269948Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.Type: GrantFiled: April 3, 2018Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Han-Chin Chiu, Sheng-De Liu, Yu-Syuan Lin, Yao-Chung Chang, Cheng-Yuan Tsai
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Publication number: 20190109223Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.Type: ApplicationFiled: November 26, 2018Publication date: April 11, 2019Inventors: Sheng-De Liu, Chung-Yen Chou, Shih-Chang Liu
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Patent number: 10141438Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. A sidewall of the first passivation layer contacting with the source region comprises a stair shape.Type: GrantFiled: March 7, 2016Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sheng-De Liu, Chung-Yen Chou, Shih-Chang Liu
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Publication number: 20180226501Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: HAN-CHIN CHIU, SHENG-DE LIU, YU-SYUAN LIN, YAO-CHUNG CHANG, CHENG-YUAN TSAI
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Publication number: 20180197856Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9941398Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.Type: GrantFiled: March 17, 2016Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Han-Chin Chiu, Sheng-De Liu, Yu-Syuan Lin, Yao-Chung Chang, Cheng-Yuan Tsai
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Patent number: 9911734Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.Type: GrantFiled: July 29, 2016Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20170271492Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.Type: ApplicationFiled: March 17, 2016Publication date: September 21, 2017Inventors: HAN-CHIN CHIU, SHENG-DE LIU, YU-SYUAN LIN, YAO-CHUNG CHANG, CHENG-YUAN TSAI
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Publication number: 20170256636Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. A sidewall of the first passivation layer contacting with the source region comprises a stair shape.Type: ApplicationFiled: March 7, 2016Publication date: September 7, 2017Inventors: SHENG-DE LIU, CHUNG-YEN CHOU, SHIH-CHANG LIU
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Patent number: 9748373Abstract: Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.Type: GrantFiled: February 1, 2016Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-De Liu, Ming-Chyi Liu, Chung-Yen Chou, Chia-Shiung Tsai
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Patent number: 9601608Abstract: A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided.Type: GrantFiled: November 13, 2014Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Wei Tsai, King-Yuen Wong, Han-Chin Chiu, Sheng-de Liu
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Patent number: 9530685Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.Type: GrantFiled: September 11, 2015Date of Patent: December 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Che-Ming Chang, Chung-Yen Chou, Chia-Shiung Tsai
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Publication number: 20160336314Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9418901Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.Type: GrantFiled: October 15, 2014Date of Patent: August 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20160163848Abstract: Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.Type: ApplicationFiled: February 1, 2016Publication date: June 9, 2016Inventors: Sheng-De Liu, Ming-Chyi Liu, Chung-Yen Chou, Chia-Shiung Tsai
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Publication number: 20160141404Abstract: A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided.Type: ApplicationFiled: November 13, 2014Publication date: May 19, 2016Inventors: Ming-Wei Tsai, King-Yuen Wong, Han-Chin Chiu, Sheng-de Liu