Patents by Inventor Shenghu Tan

Shenghu Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9142768
    Abstract: Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: September 22, 2015
    Assignee: Peking University
    Inventors: Yimao Cai, Jun Mao, Ru Huang, Shenghu Tan, Yinglong Huang, Yue Pan
  • Patent number: 8942036
    Abstract: The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: January 27, 2015
    Assignee: Peking University
    Inventors: Yimao Cai, Ru Huang, Shiqiang Qin, Poren Tang, Yu Tang, Shenghu Tan, Xin Huang, Yue Pan
  • Publication number: 20150021539
    Abstract: Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.
    Type: Application
    Filed: May 2, 2012
    Publication date: January 22, 2015
    Inventors: Yimao Cai, Jun Mao, Ru Huang, Shenghu Tan, Yinglong Huang, Yue Pan
  • Publication number: 20140145139
    Abstract: The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained.
    Type: Application
    Filed: February 22, 2012
    Publication date: May 29, 2014
    Inventors: Ru Huang, Yu Tang, Yimao Cai, Lijie Zhang, Gengyu Yang, Shenghu Tan, Yue Pan, Poren Tang
  • Patent number: 8633465
    Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 21, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
  • Publication number: 20130217199
    Abstract: The present invention discloses a method for fabricating a resistive memory, including: fabricating a bottom electrode over a substrate; partially oxidizing a metal of the bottom electrode through dry-oxygen oxidation or wet-oxygen oxidation to form a metal oxide with a thickness of 3 nm to 50 nm as a resistive material layer; finally fabricating a top electrode over the resistive material layer. The present invention omits a step of depositing a resistive material layer in a conventional method, so as to greatly reduce the process complexity. Meanwhile, a self alignment between the resistive material layer and the bottom electrode can be realized. A full isolation between devices may be ensured so as to obviate the parasite effects occurred in the conventional process methods. Meanwhile, the actual area and designed area of the device are ensured to be consistent.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 22, 2013
    Applicant: PEKING UNIVERSITY
    Inventors: Ru Huang, Shenghu Tan, Lijie Zhang, Yue Pan, Yinglong Huang, Gengyu Yang, Yu Tang, Jun Mao, Yimao Cai
  • Publication number: 20130069031
    Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
    Type: Application
    Filed: February 8, 2012
    Publication date: March 21, 2013
    Applicant: PEKING UNIVERSITY NO. 5 YIHEYUAN ROAD HAIDIAN DISTRICT
    Inventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
  • Publication number: 20120261740
    Abstract: The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel.
    Type: Application
    Filed: October 14, 2011
    Publication date: October 18, 2012
    Applicant: PEKING UNIVERSITY
    Inventors: Yimao Cai, Ru Huang, Shiqiang Qin, Poren Tang, Shenghu Tan
  • Publication number: 20120188821
    Abstract: The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.
    Type: Application
    Filed: October 14, 2011
    Publication date: July 26, 2012
    Inventors: Yimao Cai, Ru Huang, Shiqiang Qin, Poren Tang, Yu Tang, Shenghu Tan, Xin Huang, Yue Pan