Abstract: A random number sequence output apparatus (101) includes a sequence acceptance unit (102) for accepting input of a numerical sequence, an initial value setting unit (103) for accepting an initial value and causing a storage unit (104) to store this, an output unit (105) for outputting a new value stored in the storage unit (104), a calculation unit (106) for applying a predetermined rational map stored in he storage unit (104) each time the output unit (105) outputs a value and further applying a predetermined calculation unit to the value and value extracted from the numerical sequence accepted by the sequence acceptance unit (102), and an updating unit (104) to store the value of the result of calculation performed by the calculation unit (106), thereby performing updating.

Abstract: A filter (201) accepts spreading code sequences or the like as input sequences of a chip rate 1/D, the accepted spreading code sequences are sequentially delayed and distributed by delay circuits (202) connected in series, delay times of individual signals are an arithmetical progression with a chip length D being a common difference D, the individual signals are amplified with spreading codes by amplifiers (203), amplification factors for the individual signals are a geometrical progression of a common ratio r, the sum of the amplified signals is obtained by addition in an adder (204), and the result is sequentially output as an output sequence.

Abstract: A random number sequence output apparatus (101) includes a sequence acceptance unit (102) for accepting input of a numerical sequence, an initial value setting unit (103) for accepting an initial value and causing a storage unit (104) to store this, an output unit (105) for outputting a new value stored in the storage unit (104), a calculation unit (106) for applying a predetermined rational map stored in he storage unit (104) each time the output unit (105) outputs a value and further applying a predetermined calculation unit to the value and value extracted from the numerical sequence accepted by the sequence acceptance unit (102), and an updating unit (104) to store the value of the result of calculation performed by the calculation unit (106), thereby performing updating.

Abstract: A filter (201) accepts spreading code sequences or the like as input sequences of a chip rate 1/D, the accepted spreading code sequences are sequentially delayed and distributed by delay circuits (202) connected in series, delay times of individual signals are an arithmetical progression with a chip length D being a common difference D, the individual signals are amplified with spreading codes by amplifiers (203), amplification factors for the individual signals are a geometrical progression of a common ratio r, the sum of the amplified signals is obtained by addition in an adder (204), and the result is sequentially output as an output sequence.