Abstract: Methods and structures are provided for a dual-bit EEPROM semiconductor device. The dual-bit memory device comprises a semiconductor substrate, a tunnel oxide disposed on the semiconductor substrate and first and second spaced apart floating gates that are disposed on the tunnel oxide. An interlayer dielectric layer contacts the tunnel oxide layer at a position between the first and second spaced apart floating gates and electrically isolates the first and second spaced apart floating gates. A control gate contacts the interlayer dielectric layer between the first and second spaced apart floating gates.

Abstract: Various methods of inspecting a workpiece for residue are provided. In one aspect, a method of fabricating a conductor layer on a substrate is provided that includes forming an aluminum-copper film on the substrate in a first processing chamber and forming an anti-reflective coating on the aluminum-copper film in a second processing chamber. The substrate is moved from the second processing chamber into a cooling chamber to quench the substrate. A first time interval during which the substrate is in the first processing chamber and second time interval during which the substrate is present in the second processing chamber are measured. The substrate is annealed to restore a uniform equilibrium distribution of copper in the aluminum if the first time interval exceeds about 600 seconds or the second time interval exceeds about 300 seconds. The method substantially reduces the risk of metal comb bridging device failures following etch definition of conductor lines.

Abstract: A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N2O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N2O plasma is created by applying RF power to a showerhead from which the N2O is dispensed. By reacting an N2O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 Å and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N2O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N2O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N2O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation.

Abstract: Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.