Patents by Inventor Sheng-Yuan Yang

Sheng-Yuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162051
    Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 16, 2024
    Inventors: Kuo-Ming WU, Hau-Yi HSIAO, Kai-Yun YANG, Che Wei YANG, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
  • Publication number: 20240090336
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20240084455
    Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.
    Type: Application
    Filed: February 8, 2023
    Publication date: March 14, 2024
    Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
  • Publication number: 20110064631
    Abstract: A hydrogen generator essentially composed of a first medium is provided, comprising: a reforming zone, a preheating zone and a heat source. The reforming zone is used for containing a reforming catalyst so as to perform a steam reforming reaction of a hydrogen-producing raw material to generate hydrogen; and the heat source provides heat to the preheating zone and reforming zone, so that the hydrogen-producing raw material is firstly preheated in the preheating zone and then performs the steam reforming reaction in the reforming zone. The reforming zone and preheating zone are divided with a shortest interval of at least about 0.5 mm with the first medium, wherein the first medium has a thermal conductivity (K) of at least about 60 W/m-K.
    Type: Application
    Filed: December 17, 2009
    Publication date: March 17, 2011
    Inventors: Min-Hon Rei, Shih-Chung Chen, Sheng-Yuan Yang, Yu-Lin Chen, Guan-Tyng Yeh, Chia-Yeh Hung, Yu-Ling Kao
  • Publication number: 20100090284
    Abstract: A metal-oxide-semiconductor device includes a substrate, a gate on the substrate, a source in the substrate and adjacent to one side of the gate, a drain in the substrate and adjacent to another side of the gate, a gate channel in the substrate and under the gate, and a gate insulator between the source and the drain and the gate and the gate channel, wherein the gate insulator has a substantially uneven thickness for use in electrostatic discharge (ESD) protection.
    Type: Application
    Filed: November 26, 2008
    Publication date: April 15, 2010
    Inventors: Yen-Wei Liao, Sheng-Yuan Yang, Cheng-Yu Fang
  • Publication number: 20100052056
    Abstract: An ESD protection device includes a substrate with a doped well of a first conductive type, a first and a second doping region of the first conductive type and a third and a fourth doping region of a second conductive type respectively disposed in the doped well, a first gate disposed on the substrate and between the first and the second doping region, and a second gate disposed on the substrate and between the second and the third doping region to determine the distance between the second and the third doping region in order to precisely adjust the breakdown voltage of the ESD protection device of the present invention.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 4, 2010
    Inventors: Yen-Wei Liao, Sheng-Yuan Yang, Cheng-Yu Fang
  • Publication number: 20080315307
    Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.
    Type: Application
    Filed: September 4, 2008
    Publication date: December 25, 2008
    Applicant: ADVANCED ANALOG TECHNOLOGY, Inc.
    Inventors: Cheng Yu FANG, Sheng Yuan Yang, Wei Jung Chen
  • Publication number: 20080054309
    Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.
    Type: Application
    Filed: January 9, 2007
    Publication date: March 6, 2008
    Applicant: ADVANCED ANALOG TECHNOLOGY, Inc.
    Inventors: Cheng Yu Fang, Sheng Yuan Yang, Wei Jung Chen