Patents by Inventor Sherif Embabi
Sherif Embabi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9831838Abstract: A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.Type: GrantFiled: August 28, 2015Date of Patent: November 28, 2017Assignee: Nvidia CorporationInventors: Sherif Abdelhalem, Frank Zhang, Abdellatif Bellaouar, Sherif Embabi
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Publication number: 20160173042Abstract: A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.Type: ApplicationFiled: August 28, 2015Publication date: June 16, 2016Inventors: Sherif Abdelhalem, Frank Zhang, Abdellatif Bellaouar, Sherif Embabi
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Patent number: 7693236Abstract: An RF receiver apparatus (31) is provided physically separately from a cooperating baseband processor apparatus (32). The RF receiver includes a mixer circuit (33) and an analog IF-to-digital baseband converter (34) formed on an integrated circuit. Sampling frequencies of the analog IF-to-digital baseband converter are controlled by the RF receiver apparatus.Type: GrantFiled: May 8, 2001Date of Patent: April 6, 2010Assignee: Texas Instruments IncorporatedInventors: Samuel D. Pritchett, Jeffrey A. Schlang, Sherif Embabi, Alan Holden, Francesco Dantoni
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Publication number: 20070132500Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.Type: ApplicationFiled: December 12, 2005Publication date: June 14, 2007Inventors: Sherif Embabi, Alan Holden, Jason Jaehnig, Abdellatif Bellaouar
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Patent number: 7110732Abstract: A subsampling receiver (50, 50?, 50?) for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50?, 50?) may be implemented into a wireless communications device (40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes a sample and hold circuit (80) that samples a bandpass filtered input modulated signal at the subsampling frequency (fs) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver (50?) includes two sample and hold circuits (96I, 96Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components.Type: GrantFiled: March 19, 2002Date of Patent: September 19, 2006Assignee: Texas Instruments IncorporatedInventors: Mohamed A. I. Mostafa, Sherif Embabi, Moderage C. Fernando, Wing Kan Chan, Charles Gore, Jr.
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Patent number: 6646498Abstract: An integrated circuit (ICT) comprising a filter (50). The filter comprises an input (&ugr;in+) for receiving an input signal and an output (56) for producing an output signal having a frequency cutoff point. The filter further comprises at least one resistor network (RN1) coupled between the input and the output. The resistor network comprises a first non-switched resistance (R1.1) and a first resistance series connection connected in parallel with the first non-switched resistance. The first resistance series connection comprises a switched resistance (R1.2) connected in series with a source/drain path of a switching transistor (TRR1.2), the switching transistor having a gate for receiving a control signal. The frequency cutoff point is adjustable in response to the control signal. Additionally, the switched resistance has a first resistance and the switching transistor has an on-resistance. Further, the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.Type: GrantFiled: December 18, 2001Date of Patent: November 11, 2003Assignee: Texas Instruments IncorporatedInventors: Ahmed N. Mohieldin, Abdellatif Bellaouar, Sherif Embabi, Michel Frechette
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Publication number: 20030132797Abstract: An integrated circuit (ICT) comprising a filter (50). The filter comprises an input (&ngr;in+) for receiving an input signal and an output (56) for producing an output signal having a frequency cutoff point. The filter further comprises at least one resistor network (RN1) coupled between the input and the output. The resistor network comprises a first non-switched resistance (R1.1) and a first resistance series connection connected in parallel with the first non-switched resistance. The first resistance series connection comprises a switched resistance (R1.2) connected in series with a source/drain path of a switching transistor (TRR1.2), the switching transistor having a gate for receiving a control signal. The frequency cutoff point is adjustable in response to the control signal. Additionally, the switched resistance has a first resistance and the switching transistor has an on-resistance. Further, the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.Type: ApplicationFiled: December 18, 2001Publication date: July 17, 2003Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ahmed N. Mohieldin, Abdellatif Bellaouar, Sherif Embabi, Michel Frechette
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Patent number: 6545547Abstract: A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.Type: GrantFiled: August 13, 2001Date of Patent: April 8, 2003Assignee: Texas Instruments IncorporatedInventors: Ahmed Reda Fridi, Abdellatif Bellaouar, Sherif Embabi
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Publication number: 20020181614Abstract: A subsampling receiver (50, 50′, 50″) for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50′, 50″) may be implemented into a wireless communications device (40), such as a wireless telephone handset. In one disclosed embodiment, the receiver (50) includes a sample and hold circuit (80) that samples a bandpass filtered input modulated signal at the subsampling frequency (fs) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (85I, 85Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver (50′) includes two sample and hold circuits (96I, 96Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components.Type: ApplicationFiled: March 19, 2002Publication date: December 5, 2002Applicant: Texas Instruments IncorporatedInventors: Mohamed A.I. Mostafa, Sherif Embabi, Moderage C. Fernando, Wing Kan Chan, Charles Gore
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Publication number: 20020040991Abstract: A switched variable capacitor (20), and binary-weighted array (40) of such capacitors (20), are disclosed. The switched variable capacitor (20) includes a switching transistor (14) connected in series with first and second capacitors (12), between the two terminals (A,B). Bias transistors (18) are provided, and of opposite conductivity type as the switching transistor (14) but with their gates connected to the gate of the switching transistor (14). The bias transistors (18), when on, apply a reverse bias voltage to the source/drain regions of the switching transistor (14), to minimize the parasitic junction capacitance, and thus improve the temperature stability of the capacitor (20). A binary-weighted array (40) of switched variable capacitors (20) is also disclosed, as is a voltage-controlled oscillator (50) incorporating such an array (40).Type: ApplicationFiled: May 25, 2001Publication date: April 11, 2002Inventors: Sherif Embabi, Abdellatif Bellaouar
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Publication number: 20020036545Abstract: A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without the need for charge pumps. A PLL synthesizer (300) using such a PLL design provides for very fast lock times by using an open loop step and a closed loop step. The hybrid PLL can achieve coarse tuning within four clock cycles, while minimizing any errors caused by the VCO non-linearity. Temperature tracking and compensation is also provided. A SAR implementation (100) and an interpolation tuning implementation (200) are also described.Type: ApplicationFiled: August 13, 2001Publication date: March 28, 2002Inventors: Ahmed Reda Fridi, Abdellatif Bellaouar, Sherif Embabi
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Publication number: 20020009164Abstract: In an RF receiver apparatus (31) that is provided physically separately from a cooperating baseband processor apparatus (32), the frequency plan options of the RF receiver apparatus can be enhanced by integrating into the RF receiver apparatus a suitably designed digital-IF-to baseband converter.Type: ApplicationFiled: May 8, 2001Publication date: January 24, 2002Inventors: Samuel D. Pritchett, Jeffrey A. Schlang, Sherif Embabi, Alan Holden, Francesco Dantoni