Patents by Inventor Sherman H. Yip
Sherman H. Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9086889Abstract: Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.Type: GrantFiled: April 27, 2010Date of Patent: July 21, 2015Assignee: Oracle International CorporationInventors: Martin Karlsson, Sherman H. Yip, Shailender Chaudhry
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Patent number: 8984264Abstract: The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode.Type: GrantFiled: January 15, 2010Date of Patent: March 17, 2015Assignee: Oracle America, Inc.Inventors: Martin R. Karlsson, Sherman H. Yip, Shailender Chaudhry
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Patent number: 8732438Abstract: Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.Type: GrantFiled: April 16, 2008Date of Patent: May 20, 2014Assignee: Oracle America, Inc.Inventors: Paul Caprioli, Sherman H. Yip, Gideon N. Levinsky
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Patent number: 8688963Abstract: The embodiments described in the instant application provide a system for generating checkpoints. In the described embodiments, while speculatively executing instructions with one or more checkpoints in use, upon detecting an occurrence of a predetermined operating condition or encountering a predetermined type of instruction, the system is configured to determine whether an additional checkpoint is to be generated by computing a factor based on one or more operating conditions of the processor. When the factor is greater than a predetermined value, the processor is configured to generate the additional checkpoint.Type: GrantFiled: April 22, 2010Date of Patent: April 1, 2014Assignee: Oracle International CorporationInventors: Shailender Chaudhry, Martin R. Karlsson, Sherman H. Yip
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Patent number: 8572356Abstract: Techniques and structures are disclosed for a processor supporting checkpointing to operate effectively in scouting mode while a maximum number of supported checkpoints are active. Operation in scouting mode may include using bypass logic and a set of register storage locations to store and/or forward in-flight instruction results that were calculated during scouting mode. These forwarded results may be used during scouting mode to calculate memory load addresses for yet other in-flight instructions, and the processor may accordingly cause data to be prefetched from these calculated memory load addresses. The set of register storage locations may comprise a working register file or an active portion of a multiported register file.Type: GrantFiled: January 5, 2010Date of Patent: October 29, 2013Assignee: Oracle America, Inc.Inventors: Sherman H. Yip, Paul Caprioli
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Patent number: 8364900Abstract: Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate indices using the two or more indices. The system then uses at least one of the two or more indices or the two or more intermediate indices to perform a lookup in one or more lookup tables, wherein the lookup returns a value which identifies a least-recently-used way. Next, the system replaces the entry in the least-recently-used way.Type: GrantFiled: February 12, 2008Date of Patent: January 29, 2013Assignee: Oracle America, Inc.Inventors: Paul Caprioli, Sherman H. Yip, Shailender Chaudhry
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Patent number: 8327188Abstract: The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.Type: GrantFiled: November 13, 2009Date of Patent: December 4, 2012Assignee: Oracle America, Inc.Inventors: Martin R. Karlsson, Sherman H. Yip, Shailender Chaudhry
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Facilitating transactional execution in a processor that supports simultaneous speculative threading
Patent number: 8316366Abstract: Embodiments of the present invention provide a system that executes a transaction on a simultaneous speculative threading (SST) processor. In these embodiments, the processor includes a primary strand and a subordinate strand. Upon encountering a transaction with the primary strand while executing instructions non-transactionally, the processor checkpoints the primary strand and executes the transaction with the primary strand while continuing to non-transactionally execute deferred instructions with the subordinate strand. When the subordinate strand non-transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate the first strand ID. When the primary strand transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate a second strand ID.Type: GrantFiled: April 2, 2008Date of Patent: November 20, 2012Assignee: Oracle America, Inc.Inventors: Sherman H. Yip, Paul Caprioli, Marc Tremblay -
Patent number: 8181002Abstract: One embodiment of the present invention provides a system that merges checkpoints on a processor. The system starts by executing instructions speculatively during a speculative-execution episode. The system then generates a first checkpoint and a second checkpoint during the speculative-execution episode. Next, the system merges the first checkpoint with the second checkpoint during the speculative-execution episode, wherein merging the first and second checkpoints conserves processor resources.Type: GrantFiled: January 18, 2007Date of Patent: May 15, 2012Assignee: Oracle America, Inc.Inventors: Sherman H. Yip, Paul Caprioli, Marc Tremblay
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Patent number: 8065485Abstract: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.Type: GrantFiled: May 22, 2009Date of Patent: November 22, 2011Assignee: Oracle America, Inc.Inventors: Gideon N. Levinsky, Paul Caprioli, Sherman H. Yip
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Publication number: 20110264898Abstract: The embodiments described in the instant application provide a system for generating checkpoints. In the described embodiments, while speculatively executing instructions with one or more checkpoints in use, upon detecting an occurrence of a predetermined operating condition or encountering a predetermined type of instruction, the system is configured to determine whether an additional checkpoint is to be generated by computing a factor based on one or more operating conditions of the processor. When the factor is greater than a predetermined value, the processor is configured to generate the additional checkpoint.Type: ApplicationFiled: April 22, 2010Publication date: October 27, 2011Applicant: Oracle International CorporationInventors: Shailender Chaudhry, Martin R. Karlsson, Sherman H. Yip
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Publication number: 20110264862Abstract: Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.Type: ApplicationFiled: April 27, 2010Publication date: October 27, 2011Inventors: Martin Karlsson, Sherman H. Yip, Shailender Chaudhry
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Patent number: 8041900Abstract: Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.Type: GrantFiled: January 15, 2008Date of Patent: October 18, 2011Assignee: Oracle America, Inc.Inventors: Paul Caprioli, Martin Karlsson, Sherman H. Yip
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Publication number: 20110179258Abstract: The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode.Type: ApplicationFiled: January 15, 2010Publication date: July 21, 2011Applicant: SUN MICROSYSTEMS, INC.Inventors: Martin R. Karlsson, Sherman H. Yip, Shailender Chaudhry
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Publication number: 20110179254Abstract: The described embodiments relate to a processor that speculatively executes instructions. During operation, the processor often executes instructions in a speculative-execution mode. Upon detecting an impending pipe-clearing event while executing instructions in the speculative-execution mode, the processor stalls an instruction fetch unit to prevent the instruction fetch unit from fetching instructions. In some embodiments, the processor stalls the instruction fetch unit until a condition that originally caused the processor to operate in the speculative-execution mode is resolved. In alternative embodiments, the processor maintains the stall of the instruction fetch unit until the pipe-clearing event has been completed (i.e., has been handled in the processor).Type: ApplicationFiled: January 15, 2010Publication date: July 21, 2011Applicant: SUN MICROSYSTEMS, INC.Inventors: Sherman H. Yip, Martin R. Karlsson, Shailender Chaudhry
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Publication number: 20110167243Abstract: Techniques and structures are disclosed for a processor supporting checkpointing to operate effectively in scouting mode while a maximum number of supported checkpoints are active. Operation in scouting mode may include using bypass logic and a set of register storage locations to store and/or forward in-flight instruction results that were calculated during scouting mode. These forwarded results may be used during scouting mode to calculate memory load addresses for yet other in-flight instructions, and the processor may accordingly cause data to be prefetched from these calculated memory load addresses. The set of register storage locations may comprise a working register file or an active portion of a multiported register file.Type: ApplicationFiled: January 5, 2010Publication date: July 7, 2011Inventors: Sherman H. Yip, Paul Caprioli
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Publication number: 20110119528Abstract: The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.Type: ApplicationFiled: November 13, 2009Publication date: May 19, 2011Applicant: SUN MICROSYSTEMS, INC.Inventors: Martin R. Karlsson, Sherman H. Yip, Shailender Chaudhry
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Publication number: 20100299482Abstract: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.Type: ApplicationFiled: May 22, 2009Publication date: November 25, 2010Inventors: Gideon N. Levinsky, Paul Caprioli, Sherman H. Yip
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Patent number: 7757068Abstract: One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.Type: GrantFiled: January 16, 2007Date of Patent: July 13, 2010Assignee: Oracle America, Inc.Inventors: Paul Caprioli, Shailender Chaudhry, Sherman H. Yip
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Patent number: 7716457Abstract: One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.Type: GrantFiled: January 16, 2007Date of Patent: May 11, 2010Assignee: Oracle America, Inc.Inventors: Paul Caprioli, Shailender Chaudhry, Sherman H. Yip