Patents by Inventor Shesh M. Pandey
Shesh M. Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162345Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a metal field plate contact and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a shallow trench isolation structure within the semiconductor substrate; and a contact extending from the gate structure and into the shallow trench isolation structure.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Inventors: Shesh M. PANDEY, Rajendran KRISHNASAMY, Judson R. HOLT, Chung Foong TAN
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Publication number: 20240162146Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an e-fuse with metal fill structures and methods of manufacture. The structure includes: an insulator material; an e-fuse structure on the insulator material; a plurality of heaters on the insulator material and positioned on sides of the e-fuse structure; and conductive fill material within a space between the e-fuse structure and the plurality of heaters.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Inventors: Shesh M. PANDEY, Rajendran KRISHNASAMY, Vibhor JAIN
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Patent number: 10923469Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.Type: GrantFiled: January 10, 2019Date of Patent: February 16, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Hui Zang, Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen, Garo J. Derderian, Shesh M. Pandey, Laertis Economikos
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Patent number: 10741656Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.Type: GrantFiled: September 4, 2018Date of Patent: August 11, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Ruilong Xie, Shesh M. Pandey, Laertis Economikos
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Publication number: 20200227404Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.Type: ApplicationFiled: January 10, 2019Publication date: July 16, 2020Inventors: Hui Zang, Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen, Garo J. Derderian, Shesh M. Pandey, Laertis Economikos
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Publication number: 20200075738Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.Type: ApplicationFiled: September 4, 2018Publication date: March 5, 2020Inventors: Hui Zang, Ruilong Xie, Shesh M. Pandey, Laertis Economikos
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Patent number: 10374029Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.Type: GrantFiled: December 20, 2017Date of Patent: August 6, 2019Assignee: GLOBAL FOUNDRIES INC.Inventors: Hui Zang, Josef S. Watts, Shesh M. Pandey
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Patent number: 10236213Abstract: A gate cut structure for finFETs, and a related method, are disclosed. The gate cut structure separates and electrically isolates an end of a first metal gate conductor of a first finFET from an end of a second metal gate conductor of a second finFET. The gate cut structure includes a body contacting the end of the first and second metal gate conductors. A liner spacer separates a lower portion of the body from an interlayer dielectric (ILD), and an upper portion of the body contacts the ILD. During formation, the liner spacer allows for a larger gate cut opening to be used to allow quality cleaning of the gate cut opening, but also reduction in size of the spacing between metal gate conductor ends of the finFETs. In one example, the body may have a lower portion having a width less than an upper portion thereof.Type: GrantFiled: March 12, 2018Date of Patent: March 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Shesh M. Pandey, Jiehui Shu, Hui Zang, Laertis Economikos
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Publication number: 20180122891Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.Type: ApplicationFiled: December 20, 2017Publication date: May 3, 2018Inventors: Hui Zang, Josef S. Watts, Shesh M. Pandey
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Publication number: 20180083089Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.Type: ApplicationFiled: September 21, 2016Publication date: March 22, 2018Inventors: Hui Zang, Josef S. Watts, Shesh M. Pandey
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Patent number: 9923046Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.Type: GrantFiled: September 21, 2016Date of Patent: March 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Josef S. Watts, Shesh M. Pandey
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Publication number: 20140231960Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Nam Sung Kim, Roderick M. Miller, Shesh M. Pandey, Jagar Singh