Patents by Inventor Shi-An Chen

Shi-An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Patent number: 11997851
    Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 28, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiang Hui Zhao, Zui Xin Zeng, Jun Hu, Shi Zhang, Baoyou Chen
  • Publication number: 20240170230
    Abstract: A method for prelithiating a soft carbon negative electrode includes the steps of: disposing the soft carbon negative electrode and a lithium metal piece spaced apart from each other with a lithium-containing electrolyte present therebetween; prelithiating the soft carbon negative electrode at a first constant C-rate until a voltage thereof is reduced to a first predetermined voltage not greater than 0.3 V vs. Li/Li+, the first constant C-rate being not greater than 5 C; prelithiating the soft carbon negative electrode at a second constant C-rate until the voltage thereof is reduced to a second predetermined voltage lower than the first predetermined voltage, the second constant C-rate being not greater than 0.2 C and being less than the first constant C-rate; and prelithiating the soft carbon negative electrode at a prelithiation constant voltage which is not greater than the second predetermined voltage, thereby completing prelithiation of the soft carbon negative electrode.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 23, 2024
    Inventors: Yan-Shi CHEN, Guo-Hsu LU, Chi-Chang HU, Chih-Yu KU, Tien-Yu YI
  • Patent number: 11984375
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Publication number: 20240154120
    Abstract: A method for making a carbon material for an anode of a lithium-ion secondary battery includes a sequence of: a) heating a heavy hydrocarbon oil to obtain a green coke, b) a heating the green coke to form a carbon-containing material, c) grinding the carbon-containing material into a powder, and collecting a portion of the powder, d) heating the portion of the powder to obtain a carbonaceous powder, and e) adding pitch to the carbonaceous powder and heating the pitch-contained carbonaceous powder. A lithium-ion secondary battery, which includes the anode having the carbon material, is also disclosed.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 9, 2024
    Applicant: CPC CORPORATION, TAIWAN
    Inventors: Yan-Shi Chen, Guo-Hsu Lu
  • Publication number: 20240152531
    Abstract: The present disclosure proposes method and apparatus for query-based table visualization. A query may be obtained. At least one search result for the query may be obtained. A table may be extracted from the at least one search result. At least one chart corresponding to the table may be generated based on the query and the table.
    Type: Application
    Filed: April 7, 2022
    Publication date: May 9, 2024
    Inventors: Wei Ji, Yining Chen, Mengyu Zhou, Shi HAN, Daxin JIANG, Dongmei ZHANG, Elbio Renato Torres ABIB
  • Publication number: 20240153842
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20240136317
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Patent number: 11965833
    Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: April 23, 2024
    Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jing-Zhi Hou, Lin-Hui Cheng, Yan-Chao Ma, Jin-Cai Zhou, Zi-Long Ma, Neng-Neng Zhang, Yi Chen, Chen-Xi Tang, Meng Lu, Peng Zhou, Ling-Hui Zhang, Lu-Hui Fan, Shi-Gang Xu, Cheng-Yi Chao, Liang-Yi Lu
  • Publication number: 20240128217
    Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.
    Type: Application
    Filed: January 20, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung CHEN, Chen Chiang YU, Wei-An TSAO, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Patent number: 11961777
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11961814
    Abstract: In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Shou-Yi Wang, Jiun Yi Wu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240116655
    Abstract: Disclosed are a system and a method for capturing a space target. The system includes a plurality of capturing devices, a delivery device, a launching device, and a deceleration and recovery device, each of the plurality of capturing devices is configured to be launched into a target orbit to capture a defunct space target, the delivery device is configured to deliver, along a preset delivery trajectory, each of the plurality of capturing devices to a first preset location in the launching device, the launching device is configured to launch each of the plurality of capturing devices located at the first preset location into the target orbit to capture the defunct space target, and the deceleration and recovery device is configured to decelerate each of the plurality of capturing devices after it is launched and flies a preset distance.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Applicant: Harbin Institute of Technology
    Inventors: Jinsheng GUO, Fan WU, Shi QIU, Jian CHEN, Cheng WEI, Hongxu WANG
  • Patent number: 11955460
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20240100209
    Abstract: A sterilization and deodorization waste container having dual-wave band ultraviolet lamp tube includes an isolation chamber provided on an inner side of a container lid and a dual-wave band ultraviolet lamp tube installed in the isolation chamber. The dual-wave band ultraviolet lamp tube is capable of simultaneously generating a direct ultraviolet light wave and an ozone ultraviolet light wave. The isolation chamber includes a reflector housing having a light transmitting window facing an inner cavity of a container body. The dual-wave band ultraviolet lamp tube is controlled by a control circuit to turn on to generate the ultraviolets into an inner cavity of the container body while the container lid is closed and to turn off to stop generating the ultraviolet while the container lid is opened.
    Type: Application
    Filed: July 30, 2021
    Publication date: March 28, 2024
    Applicants: Fujian Nashida Electronic Incorporated Company, Nine Stars Group (U.S.A.) Inc.
    Inventors: Shi Ping Wang, Jiangqun Chen, Youxi Lou, Zhou Lin
  • Patent number: 11939603
    Abstract: A modified cutinase is disclosed. The cutinase has the modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of asparagine at position 181 with alanine, or substitutions of asparagine at position 181 with alanine and phenylalanine at position 235 with leucine. The modified enzyme has improved PET-hydrolytic activity, and thus, the high-activity PET hydrolase is obtained, and the industrial application value of the PET hydrolase is enhanced.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: March 26, 2024
    Assignee: HUBEI UNIVERSITY
    Inventors: Chun-Chi Chen, Jian-Wen Huang, Jian Min, Xian Li, Beilei Shi, Panpan Shen, Yu Yang, Yumei Hu, Longhai Dai, Lilan Zhang, Yunyun Yang, Rey-Ting Guo
  • Patent number: 11940498
    Abstract: Passive monitoring the integrity of current sensing devices and associated circuitry in GFCI and AFCI protective devices is provided. A protection circuit interrupter employs a capacitively coupled noise signal obtained by an arrangement of one or both of line side arms relative to a Rogowski coil. The noise signal is monitored while the line and load sides of a protective circuit interrupter are disconnected, and the connection of the line and load sides disabled if the noise signal fails to correlate sufficiently to a reference noise cycle. When the line and load sides are connected, the RMS value of the observed current signal is monitored such that the line and load sides are disconnected if the observed current signal fails to meet an RMS threshold. The observed current signal is compensated by subtracting the reference noise cycle prior to monitoring for the fault condition applicable to the protective device.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: March 26, 2024
    Assignee: Hubbell Incorporated
    Inventors: Gary Michael Miller, William Vernon Miller, Edward Shi Chen
  • Patent number: 11942464
    Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240095467
    Abstract: Translating applications to a target language includes extracting program integrated information (PII) to be translated and creating translation context datasets based on interpretation of accessibility information associated with particular strings of PII. Translation pairs include PII and corresponding context datasets for context-based translation of application components. A two-stage index contains PII strings for first stage lookup and context datasets for distinguishing duplicate PII strings as a second stage lookup. Real-time translation is facilitated by the two-stage index, which is established by translation pairs and resulting translations.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: CHIH-YUAN LIN, Jin Shi, Shu-Chih Chen, PEI-YI LIN, Chao Yuan Huang
  • Publication number: 20240087915
    Abstract: A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. The pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yen-Hao HUANG, Chun-Yi CHEN, I-Shi WANG, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN