Patents by Inventor Shi-Hao Chen
Shi-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194735Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.Type: ApplicationFiled: February 23, 2024Publication date: June 13, 2024Inventors: GUAN-LIN CHEN, KUO-CHENG CHIANG, CHIH-HAO WANG, SHI NING JU, JUI-CHIEN HUANG
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Patent number: 12009261Abstract: A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.Type: GrantFiled: November 5, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
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Patent number: 11996410Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.Type: GrantFiled: December 12, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chien Cheng, Chih-Hao Wang, Guan-Lin Chen, Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng
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Patent number: 11990471Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.Type: GrantFiled: August 10, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
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Publication number: 20240162227Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.Type: ApplicationFiled: November 19, 2023Publication date: May 16, 2024Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
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Patent number: 11984488Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.Type: GrantFiled: April 30, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
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Publication number: 20240154043Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.Type: ApplicationFiled: January 2, 2024Publication date: May 9, 2024Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240145540Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.Type: ApplicationFiled: January 20, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Guan-Lin CHEN, Jung-Chien CHENG, Chih-Hao WANG
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Patent number: 11942513Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.Type: GrantFiled: January 10, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
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Patent number: 11942478Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.Type: GrantFiled: May 6, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
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Publication number: 20240096942Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
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Publication number: 20240096895Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
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Patent number: 10145896Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.Type: GrantFiled: April 23, 2015Date of Patent: December 4, 2018Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shi-Hao Chen, Yung-Sheng Fang
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Patent number: 10125522Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.Type: GrantFiled: August 17, 2016Date of Patent: November 13, 2018Assignee: Hampton Products International CorporationInventors: Xin Ben Ou, Xin Min Ou, Han Gui Xiao, Zhi Man Yuan, Shi Hao Chen, Guo Hua Liu
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Patent number: 10047550Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.Type: GrantFiled: November 5, 2015Date of Patent: August 14, 2018Assignee: Hampton Products International CorporationInventors: Xin Ben Ou, Xin Min Ou, Han Gui Xiao, Zhi Man Yuan, Shi Hao Chen, Guo Hua Liu
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Patent number: 9606172Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.Type: GrantFiled: October 28, 2014Date of Patent: March 28, 2017Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shi-Hao Chen, Yi-Ming Wang, Ting-Hao Wang, Hung-Chun Li
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Publication number: 20160356060Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Applicant: Hampton Products International CorporationInventors: Xin Ben Ou, Xin Min Ou, Han Gui Xiao, Zhi Man Yuan, Shi Hao Chen, Guo Hua Liu
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Patent number: 9513659Abstract: An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.Type: GrantFiled: May 20, 2015Date of Patent: December 6, 2016Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Tai Wang, Shi-Hao Chen, Ming-Jing Ho
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Patent number: 9447610Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.Type: GrantFiled: September 16, 2013Date of Patent: September 20, 2016Assignee: Hampton Products International CorporationInventors: Xin Ben Ou, Xin Min Ou, Han Gui Xiao, Zhi Man Yuan, Shi Hao Chen, Guo Hua Liu
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Publication number: 20160053522Abstract: A lockset is actuable by pivoting a handle about a longitudinal axis of the lockset by rotating the handle and by pivoting the handle about an axis transverse to the lockset axis, such as by pushing or pulling. The lockset includes an inside handle and an outside handle, each associated with an independent mechanism, each of which can independently actuate the lockset. A locking mechanism prevents actuation of a first one of the independent handle mechanisms without affecting operation of the other handle mechanism. Upon actuation of the other handle mechanism, a retractor engages a surface of the locking mechanism and removes it from engagement with the first locking mechanism. An adjustment ring has a first configuration that centers the lockset in a door having a first standard thickness and a second configuration that centers the lockset in a door having a second standard thickness.Type: ApplicationFiled: November 5, 2015Publication date: February 25, 2016Applicant: Hampton Products International CorporationInventors: Xin Ben Ou, Xin Min Ou, Han Gui Xiao, Zhi Man Yuan, Shi Hao Chen, Guo Hua Liu