Abstract: The differential value of the adjacent pixels is calculated firstly and is coded by a VLC coding. The VLC coding includes codes representing the Quotient and Remainder with a marker bit inserted in between. The divider is predicted with no code in the coded data stream. If three pixel components are presented in the same clock time, three VLC encoders and three VLD decoders are applied to encode and decode one pixel at a time. During encoding, both Remainder and Quotient of the same pixel component are encoded in parallel followed. During decoding, both Remainder and Quotient of the same pixel component are decoded in parallel and the results of the first pixel component are used a reference to decode the second pixel component which adopts the same decoding procedure and the decoded results of the second pixel component is used as reference to decode the third pixel component.

Abstract: A method of demodulating a square root for processing digital signals is disclosed. The demodulation includes the following steps. First, define |l arg e| to be the larger one between the absolute value of two input values I and Q and define |small| to be the smaller one between the absolute value of the two input values I and Q. Next, define a first determining form by the inequalities 16|small?16|l arg e|?18|small| and 16|l arg e|=16|small|. In addition, define a second determining form by the inequalities 16|small|?16|l arg e|?18|small| and 16|l arg e|?|small|. When the relation between |l arg e| and |small| conforms to the first determining form, the approximate root-mean-square value of the two input values I and Q is |l arg e|+2?5|l arg e|. When the relation between |l arg e| and |small| conforms to the second determining form, the approximate root-mean-square value of the two input values I and Q is |l arg e|+2?6|l arg e|.

Abstract: An extendable squarer for processing digital signals, suitable for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n?1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.

Abstract: The differential value of the adjacent pixels is calculated firstly and is coded by a VLC coding. The VLC coding includes codes representing the Quotient and Remainder with a marker bit inserted in between. The divider is predicted with no code in the coded data stream. If three pixel components are presented in the same clock time, three VLC encoders and three VLD decoders are applied to encode and decode one pixel at a time. During encoding, both Remainder and Quotient of the same pixel component are encoded in parallel followed. During decoding, both Remainder and Quotient of the same pixel component are decoded in parallel and the results of the first pixel component are used a reference to decode the second pixel component which adopts the same decoding procedure and the decoded results of the second pixel component is used as reference to decode the third pixel component.

Abstract: The present invention provides method of a variable length coding for data compression. The first coding algorithm is applied to encode the data with the value less than half of the calculated divider and another coding algorithm encoding the subtracted value of the data. Another algorithm applies at least two predetermined “marker bits” to indicate the range of data with concatenated binary code encoding the shifted value of the data. Another algorithm deciding the boundary separating the first range and other ranges of the data and encode the data by applying at least two different algorithms accordingly.

Abstract: The present invention provides method of a variable length coding for data compression. The first coding algorithm is applied to encode the data with the value less than half of the calculated divider and another coding algorithm encoding the subtracted value of the data. Another algorithm applies at least two predetermined “marker bits” to indicate the range of data with concatenated binary code encoding the shifted value of the data. Another algorithm deciding the boundary separating the first range and other ranges of the data and encode the data by applying at least two different algorithms accordingly.

Abstract: An extendable squarer applied for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n?1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.

Abstract: A method for demodulating a square root is disclosed. The demodulation comprises the following steps. First, define |large| to be the larger one between the absolute value of two input values I and Q and define |small| to be the smaller one between the absolute value of the two input values I and Q. Next, define a first determining form by the inequalities 16|small|?16|large|?18|small| and 16|large|=16|small|. In addition, define a second determining form by the inequalities 16|small|?16|large|?18|small| and 16|large|?16|small|. When the relation between |large| and |small| conforms to the first determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2?5|large|. When the relation between |large| and |small| conforms to the second determining form, the approximate root-mean-square value of the two input values I and Q is |large|+2?6|large|.