Abstract: A method of converting a traditional staircase into a dual-use staircase, for reducing the stepping height and knee stress in stairs climbing and descending, comprises: providing a plurality of lifting modules and a plurality of extending modules; connecting the plurality of lifting and extending modules in pairs to the original steps respectively; and optionally connecting a plurality of dividers in between said lifting and extending modules respectively. The dual-use staircase structure reduces the step rise by half, while keeping the total run about the same. It allows healthy people to walk in a full-step domain, while allowing people with knee concerns to walk on a half-step domain. The dual-use staircase may include dividers with lateral openings to facilitate reverse turning halfway during ascending or descending of the staircase.

Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.

Abstract: A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power to the internal electronic circuits. A plurality of metal lines of a second metal layer of the chip are configured by an automatic place and route (APR) process according to the internal electronic circuits, and at least one sparse area is formed on the second metal layer. Later, at least one supply-power area is configured in the sparse area, and is electrically connected to the power bus.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. One or more islands are distributed either symmetrically or non-symmetrically in and along the drain region. The islands can be formed of polysilicon or a field oxide.

Abstract: An electrostatic discharge protection device formed on a substrate. The electrostatic discharge protection device includes a first isolation region formed over the substrate, an active region formed over the substrate and enclosed by the first isolation region, a second isolation region formed on the substrate and substantially surrounded by the active region, a first gate element formed in the active region, the first gate element having a first end extending over the first isolation region and a second end extending over the second isolation region, a drain region formed in the active region at a first side of the first gate element, a source region formed in the active region at a second side of the first gate element, a drain contact for electrically coupling the drain region to a first node, and a source contact for electrically coupling the source region to a second node.

Abstract: An output buffer with a pull down circuit. The pull down circuit is coupled between a second power line and a pad, and has a resistor, a diode and an electrostatic discharge protection component. The resistor deposited on the substrate of a first conductivity type includes a well region of a second conductivity type. The resistor and the electrostatic discharge protection component are connected in series between the pad and the second power line. The diode is formed in the well region, construct by the PN junction formed between a first doped region of the first conductivity type and the well region. The first doped region is electrically floated in the well regions. During an electrostatic discharge event, the pad is instantaneously connected to the first doped region which will help to boost the turn-on of the electrostatic discharge circuit, and further enhance the electrostatic protection effect.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 ? and less.

Abstract: A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power to the internal electronic circuits. A plurality of metal lines of a second metal layer of the chip are configured by an automatic place and route (APR) process according to the internal electronic circuits, and at least one sparse area is formed on the second metal layer. Later, at least one supply-power area is configured in the sparse area, and is electrically connected to the power bus.

Abstract: A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

Abstract: A method of operating a non-volatile memory device includes providing the non-volatile memory device with a body of first conductivity, a source region of second conductivity, a drain region of second conductivity on the body, and a control gate over the body adjacent to the source and drain regions. A first voltage of first polarity is applied to the control gate. A second voltage of first polarity is applied to the drain region, the second voltage being less than about 5.6 volts. A third voltage of second polarity is applied to the source region.

Abstract: An electrostatic discharge (ESD) protection device with enhanced ESD robustness. The ESD protection device comprises a pad, a finger-type MOS, a well stripe and a doped segment. The pad is on a semiconductor substrate of a first-conductive type. The finger-type MOS is on the semiconductor substrate and comprises drain regions, source regions and channel regions. Each drain region is of a second-conductive type and is coupled to the pad. Each source region is of the second-conductive type and coupled to a power rail. Channel regions are formed on the semiconductor, substantially parallel to each other. Each channel region is located between one source region and one drain region. The well stripe is of the second-conductive type and formed on the semiconductor, in an angle to the channel regions. The doped segment is of the first-conductive type and in the well stripe. Furthermore, the doped segment is coupled to the pad.

Abstract: An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-to-gate-spacing (DCGS) for the PMOS can be smaller than the DCGS for the NMOS.

Abstract: An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-to-gate-spacing (DCGS) for the PMOS can be smaller than the DCGS for the NMOS.

Abstract: A method of processing memory, suitable for loading an executable object code compiled from a source code into the memory that includes defective memory cells. At first, set up a plurality of pre-compiled object codes that correspond to a source code, each pre-compiled object code having at least a skipped-code-address range. Then, test the memory and locate the defective addresses therein. According to the result of the test, the code-loading system selects an executable object that has the matching skipped-code-address range from the pre-compiled object codes, and loads the executable code into the memory. Since the skipped-code-address range covers the defective addresses in the memory, the defective memory cells in the memory won't affect the operation of loading a program.

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.