Abstract: Provided are a parasitic capacitance detection method, a memory, and a readable storage medium, relating to the field of semiconductor technologies. The detection method comprises: providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein; determining a capacitance between the wire per unit length and the gate in the semiconductor device, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length; determining a corresponding wire length of a to-be-detected semiconductor device; and determining a parasitic capacitance of the to-be-detected semiconductor device.

Abstract: Methods for measuring a temperature of a wafer chuck and calibrating temperature and a temperature measuring system are provided. The measuring method includes: placing a test wafer on a wafer chuck, where a plurality of semiconductor devices having electrical parameters varying as a function of temperature are formed on the test wafer; making the temperature of the wafer chuck reach set temperatures; measuring the semiconductor devices respectively to obtain electrical parameters corresponding to the semiconductor devices; obtaining actual temperatures of the semiconductor devices according to the electrical parameters and variations, of the electrical parameters, as the function of temperature; and obtaining an actual temperature distribution of the wafer chuck according to the actual temperatures of the semiconductor devices.

Abstract: Embodiments of the present application provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate, with word lines arranged at intervals in the substrate, and trenches between adjacent word lines; a bit line contact layer, wherein the bottom surface of the bit line contact layer is in contact with the bottom surface of the trench, and the bit line contact layer has a non-planar contact portion in the direction away from the bottom surface of the trench; the conductive layer is in contact with the non-planar contact portion of the bit line contact layer. The embodiments of the present application are beneficial in reducing the resistance of the bit line itself including the bit line contact layer and the conductive layer, thereby helping to improve the electrical performance of the semiconductor structure.

Abstract: Provided are a parasitic capacitance detection method, a memory, and a readable storage medium, relating to the field of semiconductor technologies. The detection method comprises: providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein; determining a capacitance between the wire per unit length and the gate in the semiconductor device, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length; determining a corresponding wire length of a to-be-detected semiconductor device; and determining a parasitic capacitance of the to-be-detected semiconductor device.

Abstract: Methods for measuring a temperature of a wafer chuck and calibrating temperature and a temperature measuring system are provided. The measuring method includes: placing a test wafer on a wafer chuck, where a plurality of semiconductor devices having electrical parameters varying as a function of temperature are formed on the test wafer; making the temperature of the wafer chuck reach set temperatures; measuring the semiconductor devices respectively to obtain electrical parameters corresponding to the semiconductor devices; obtaining actual temperatures of the semiconductor devices according to the electrical parameters and variations, of the electrical parameters, as the function of temperature; and obtaining an actual temperature distribution of the wafer chuck according to the actual temperatures of the semiconductor devices.

Abstract: A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density.

Abstract: A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein- the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density