Abstract: A reduced oxide stress cascode stack circuit includes a cascade transistor stack and dynamic bias circuits that supply an output voltage having a magnitude greater than an oxide reliability voltage of their component transistors. The reduced oxide stress cascode stack circuit also includes an offset voltage generator that provides an offset voltage based on a transient extreme of the output voltage, wherein the offset voltage is applied to the cascade transistor stack and the dynamic bias circuits to reduce component transistor voltages commensurate with the oxide reliability voltage. The reduced oxide stress cascode stack circuit further includes a bias voltage supply that modifies a bias voltage value of the cascade transistor stack and dynamic bias circuits by an amount proportional to the offset voltage. A method of reducing oxide stress in a cascode stack circuit is also provided.

Abstract: A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage.

Abstract: A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage.

Abstract: A system and method for maintaining values on output pads of an integrated circuit during entry, exit, and while a portion of the integrated circuit is in a power conservation or deep power down mode. The method for entering a power conservation mode includes determining a power conservation mode value which will be maintained at an output pad while a portion of an integrated circuit is in a power conservation mode. The power conservation mode value may then be selected for output and the power conservation mode value is held at the output pad. The portion of the integrated circuit to enter the power conservation mode is then electrically decoupled from the output pad. The portion of the integrated circuit may then be placed in the power conservation mode without output signal slighting while maintaining the output value.

Abstract: Embodiments for providing a plurality of bias voltages to input/output circuitry are disclosed.