Abstract: A signal output circuit includes: a driver circuit including a variable current source and configured to output a multilevel signal; a replica circuit having a circuit configuration equivalent to the driver circuit; and a control circuit configured to control a characteristic of the driver circuit, based on an output signal of the replica circuit, wherein the replica circuit includes: a first replica circuit part configured to output first output signals having signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal; and a second replica circuit part configured to output second output signals having signal levels of a second subset of the plurality of signal levels, and the control circuit is configured to control a characteristic of the variable current source, based the first output signals and the second output signals.

Abstract: A signal output circuit includes: a driver circuit including a variable current source and configured to output a multilevel signal; a replica circuit having a circuit configuration equivalent to the driver circuit; and a control circuit configured to control a characteristic of the driver circuit, based on an output signal of the replica circuit, wherein the replica circuit includes: a first replica circuit part configured to output first output signals having signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal; and a second replica circuit part configured to output second output signals having signal levels of a second subset of the plurality of signal levels, and the control circuit is configured to control a characteristic of the variable current source, based the first output signals and the second output signals.

Abstract: A level shifting circuit includes a first inverter, a second inverter, and a third inverter which are connected in a cascade. The first inverter operates at a first power supply voltage supplied to a first power supply line, and the third inverter operates at a second power supply supplied to a second power supply line. The second inverter includes a first p-type transistor having a source connected to the first power supply line, a second p-type transistor having a source connected to the second power supply line, and a first n-type transistor having a source connected to a ground line. Each gate of the first and second p-type transistors and the first n-type transistor is connected to an output terminal of the first inverter, and each drain of the first and second p-type transistors and the first n-type transistor is connected to an input terminal of the third inverter.

Abstract: A signal output circuit includes: a driver circuit including a variable current source and configured to output a multilevel signal; a replica circuit having a circuit configuration equivalent to the driver circuit; and a control circuit configured to control a characteristic of the driver circuit, based on an output signal of the replica circuit, wherein the replica circuit includes: a first replica circuit part configured to output first output signals having signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal; and a second replica circuit part configured to output second output signals having signal levels of a second subset of the plurality of signal levels, and the control circuit is configured to control a characteristic of the variable current source, based the first output signals and the second output signals.

Abstract: A transmission circuit includes: a data generating circuit configured to generate data based on a clock signal; a clock generating circuit configured to supply the clock signal to the data generating circuit; and a duty ratio controlling circuit configured to detect a duty cycle distortion of the data output from the data generating circuit, and control a duty ratio of the clock signal based on a result of the detection.

Abstract: A level shifting circuit includes a first inverter, a second inverter, and a third inverter which are connected in a cascade. The first inverter operates at a first power supply voltage supplied to a first power supply line, and the third inverter operates at a second power supply supplied to a second power supply line. The second inverter includes a first p-type transistor having a source connected to the first power supply line, a second p-type transistor having a source connected to the second power supply line, and a first n-type transistor having a source connected to a ground line. Each gate of the first and second p-type transistors and the first n-type transistor is connected to an output terminal of the first inverter, and each drain of the first and second p-type transistors and the first n-type transistor is connected to an input terminal of the third inverter.

Abstract: A signal output circuit includes: a driver circuit including a variable current source and configured to output a multilevel signal; a replica circuit having a circuit configuration equivalent to the driver circuit; and a control circuit configured to control a characteristic of the driver circuit, based on an output signal of the replica circuit, wherein the replica circuit includes: a first replica circuit part configured to output first output signals having signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal; and a second replica circuit part configured to output second output signals having signal levels of a second subset of the plurality of signal levels, and the control circuit is configured to control a characteristic of the variable current source, based the first output signals and the second output signals.

Abstract: A transmission circuit includes: a data generating circuit configured to generate data based on a clock signal; a clock generating circuit configured to supply the clock signal to the data generating circuit; and a duty ratio controlling circuit configured to detect a duty cycle distortion of the data output from the data generating circuit, and control a duty ratio of the clock signal based on a result of the detection.

Abstract: There are provided a transformer including inductors, and variable capacitors. Capacitance values of the variable capacitors are controlled by a control signal. One end of the first inductor is connected to a reference potential, the first variable capacitor is connected in series between the other end of the first inductor and a first terminal, the second variable capacitor is connected in series between one end of the second inductor and a second terminal, the third variable capacitor is connected in series between the other end of the second inductor and a third terminal. The capacitance values of the variable capacitors are changed by the control signal to obtain a desired pass phase, a loss is small, and both functions of a single-phase-differential conversion and a phase shifter are realized.

Abstract: A clock transmission circuit includes a first buffer, a second buffer, and an inductor unit. The first buffer is configured to receive a first clock which is one of differential clocks, and to buffer and output the first clock to a first clock wiring. The second buffer is configured to receive a second clock which is the other of the differential clocks, and to buffer and output the second clock to a second clock wiring. The inductor unit is connected between a first node of the first clock wiring and a second node of the second clock wiring, and configured to include a center tap to which a common voltage is applied.

Abstract: A transmitter circuit includes: a driver that includes an output resistor set to a resistance value according to an input code, and that outputs, to an output terminal, an output signal; and a high potential side resistor and a low potential side resistor that are connected to the output terminal. The transmitter circuit further includes a high potential side current source that is set with a current value according to the input code, and a low potential side current source that is set with a current value according to the input code. The transmitter circuit further includes a high potential side switch and a low potential side switch that switch between allowing current output from the high voltage side current source and the low voltage side current source to pass, and blocking the current.

Abstract: A clock transmission circuit includes a first buffer, a second buffer, and an inductor unit. The first buffer is configured to receive a first clock which is one of differential clocks, and to buffer and output the first clock to a first clock wiring. The second buffer is configured to receive a second clock which is the other of the differential clocks, and to buffer and output the second clock to a second clock wiring. The inductor unit is connected between a first node of the first clock wiring and a second node of the second clock wiring, and configured to include a center tap to which a common voltage is applied.

Abstract: A transmitter circuit includes: a driver that includes an output resistor set to a resistance value according to an input code, and that outputs, to an output terminal, an output signal; and a high potential side resistor and a low potential side resistor that are connected to the output terminal. The transmitter circuit further includes a high potential side current source that is set with a current value according to the input code, and a low potential side current source that is set with a current value according to the input code. The transmitter circuit further includes a high potential side switch and a low potential side switch that switch between allowing current output from the high voltage side current source and the low voltage side current source to pass, and blocking the current.

Abstract: There are provided a transformer including inductors, and variable capacitors. Capacitance values of the variable capacitors are controlled by a control signal. One end of the first inductor is connected to a reference potential, the first variable capacitor is connected in series between the other end of the first inductor and a first terminal, the second variable capacitor is connected in series between one end of the second inductor and a second terminal, the third variable capacitor is connected in series between the other end of the second inductor and a third terminal. The capacitance values of the variable capacitors are changed by the control signal to obtain a desired pass phase, a loss is small, and both functions of a single-phase-differential conversion and a phase shifter are realized.