Patents by Inventor Shigefumi Irieda
Shigefumi Irieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10089241Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.Type: GrantFiled: September 12, 2016Date of Patent: October 2, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tokumasa Hara, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
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Patent number: 10049760Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.Type: GrantFiled: March 15, 2017Date of Patent: August 14, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Tomoaki Nakano, Shigefumi Irieda, Masashi Yoshida
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Patent number: 9928915Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.Type: GrantFiled: October 21, 2016Date of Patent: March 27, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
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Publication number: 20180068739Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.Type: ApplicationFiled: March 15, 2017Publication date: March 8, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro SHIINO, Tomoaki NAKANO, Shigefumi IRIEDA, Masashi YOSHIDA
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Patent number: 9865338Abstract: A controller executes a first data conversion for write data to be written into a first page. The first data conversion includes increasing a ratio of a number of a first value to a total number of pieces of data. The controller executes a second data conversion for write data to be written into a second page. The second data conversion includes increasing a ratio of the number of the second value to the total number of pieces of data.Type: GrantFiled: March 3, 2016Date of Patent: January 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tokumasa Hara, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda
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Publication number: 20170262379Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.Type: ApplicationFiled: September 12, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tokumasa HARA, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
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Patent number: 9633720Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, and a third memory cell, a first word line coupled to the first memory cell, the second memory cell, and the third memory cell, a first bit line coupled to the first memory cell, a second bit line coupled to the second memory cell, and a third bit line coupled to the third memory cell. A first voltage, a second voltage, and a third voltage are sequentially applied to the first word line, and a fourth voltage is applied to the first bit line when the first voltage is applied to the first word line, applied to the second bit line when the second voltage is applied to the first word line, and applied to the third bit line when the third voltage is applied to the first word line.Type: GrantFiled: December 21, 2015Date of Patent: April 25, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki Nakano, Shigefumi Irieda, Masashi Yoshida
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Publication number: 20170076788Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, and a third memory cell, a first word line coupled to the first memory cell, the second memory cell, and the third memory cell, a first bit line coupled to the first memory cell, a second bit line coupled to the second memory cell, and a third bit line coupled to the third memory cell. A first voltage, a second voltage, and a third voltage are sequentially applied to the first word line, and a fourth voltage is applied to the first bit line when the first voltage is applied to the first word line, applied to the second bit line when the second voltage is applied to the first word line, and applied to the third bit line when the third voltage is applied to the first word line.Type: ApplicationFiled: December 21, 2015Publication date: March 16, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki NAKANO, Shigefumi IRIEDA, Masashi YOSHIDA
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Publication number: 20170060482Abstract: According to one embodiment, a controller executes a first data conversion for write data to be written into a first page. The first data conversion includes increasing a ratio of a number of a first value to a total number of pieces of data. The controller executes a second data conversion for write data to be written into a second page.Type: ApplicationFiled: March 3, 2016Publication date: March 2, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tokumasa HARA, Kiichi TACHI, Susumu TAMON, Shigefumi IRIEDA
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Publication number: 20170040062Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHIINO, Daisuke KOUNO, Shigefumi IRIEDA, Kenri NAKAI, Eietsu TAKAHASHI
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Patent number: 9508442Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.Type: GrantFiled: January 7, 2016Date of Patent: November 29, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
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Publication number: 20160196062Abstract: According to one embodiment, a memory system is connectable to an external device. The memory system includes a non-volatile memory, a control unit, and a temperature detector. The control unit is configured to manage the count information relating to a count of writes or a count of erases in the non-volatile memory in each predetermined region in the non-volatile memory. The temperature detector is configured to detect a first temperature in the memory system. The control unit is configured to add a value to the count information. The added value corresponds to the count of writes or the count of erases occurred after a previous update of the count information and the first temperature. The control unit is configured to determine a degree of deterioration of the non-volatile memory based on the count information after the addition.Type: ApplicationFiled: March 11, 2015Publication date: July 7, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Daisuke NAKATA, Hironori KATSURAYAMA, Shigefumi IRIEDA
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Publication number: 20160118127Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.Type: ApplicationFiled: January 7, 2016Publication date: April 28, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
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Patent number: 9263140Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.Type: GrantFiled: May 15, 2014Date of Patent: February 16, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
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Patent number: 9105336Abstract: A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ?Vn and when a condition of L<M (L and M are integers) is satisfied, the data writing unit executes the write loop using the passage voltage where ?V(L?1)<?VL, ?VL??V(M?1), and ?V(M?1)<?VM.Type: GrantFiled: December 7, 2012Date of Patent: August 11, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Shigefumi Irieda
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Patent number: 9047958Abstract: A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ?Vn and when a condition of L<M (L and M are integers) is satisfied, the data writing unit executes the write loop using the passage voltage where ?V(L?1)<?VL, ?VL??V(M?1), and ?V(M?1)<?VM.Type: GrantFiled: December 7, 2012Date of Patent: June 2, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Shigefumi Irieda
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Patent number: 8953371Abstract: A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates. In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.Type: GrantFiled: March 20, 2012Date of Patent: February 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi, Koki Ueno
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Patent number: 8848447Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.Type: GrantFiled: September 7, 2011Date of Patent: September 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
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Publication number: 20140254282Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.Type: ApplicationFiled: May 15, 2014Publication date: September 11, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHIINO, Daisuke KOUNO, Shigefumi IRIEDA, Kenri NAKAI, Eietsu TAKAHASHI
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Patent number: 8767477Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.Type: GrantFiled: April 17, 2013Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koki Ueno, Eietsu Takahashi, Shigefumi Irieda, Yasuhiro Shiino, Manabu Sakaniwa