Abstract: A semiconductor device includes first and second protection circuits. The first protection circuit includes a timer circuit, a voltage detection circuit, and a discharge element. The second protection circuit includes a discharge circuit. The timer circuit is connected between a first pad on a power supply potential side and a second pad on a reference potential side. The voltage detection circuit is connected between the first and second pads on an output side of the timer circuit. The discharge element is connected between the first and second pads on an output side of the voltage detection circuit. The discharge circuit is connected between a third pad on the power supply potential side and a fourth pad on the reference potential side on the output side of the timer circuit.

Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

Abstract: A semiconductor device includes first and second protection circuits. The first protection circuit includes a timer circuit, a voltage detection circuit, and a discharge element. The second protection circuit includes a discharge circuit. The timer circuit is connected between a first pad on a power supply potential side and a second pad on a reference potential side. The voltage detection circuit is connected between the first and second pads on an output side of the timer circuit. The discharge element is connected between the first and second pads on an output side of the voltage detection circuit. The discharge circuit is connected between a third pad on the power supply potential side and a fourth pad on the reference potential side on the output side of the timer circuit.

Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.

Abstract: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

Abstract: A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.

Abstract: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.

Abstract: A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.

Abstract: A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit.

Abstract: A semiconductor device includes a first input terminal, the first input terminal being supplied with an input signal, an input detection circuit including a delay circuit having a second input terminal and an output terminal, the input detection circuit detecting a shift in the input signal and generating a first pulse signal in response to the shift, the input detection circuit being connected to the first input terminal, and a control circuit for generating control signals, each of the control signals being generated in response to a synchronous operation or an asynchronous operation respectively.

Abstract: A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit.

Abstract: A semiconductor device includes a first input terminal, the first input terminal being supplied with an input signal, an input detection circuit including a delay circuit having a second input terminal and an output terminal, the input detection circuit detecting a shift in the input signal and generating a first pulse signal in response to the shift, the input detection circuit being connected to the first input terminal, and a control circuit for generating control signals, each of the control signals being generated in response to a synchronous operation or an asynchronous operation respectively.

Abstract: There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential.

Abstract: In an electrically programmable ROM, each cell 13 includes a series-connected element composed of a combination writing and reading transistor 17 and a fuse 15. One end of this series-connected element is connected to a corresponding bit line 19, and the other end thereof is grounded. A gate of the transistor 17 of the series-connected element is connected to a corresponding word line 23. Each bit line 19 is connected to a high-voltage applying pad 21 via an element such as diode or transistor provided with electrically connecting/isolating functions. When a data is written in the memory cell 13, the high-voltage applying pad 21 is electrically connected to the bit line 19. Under these conditions, if a high voltage is applied to the high-voltage applying pad 21, the transistor 17 performs snap-back action (i.e. secondary breakdown) to blow out the fuse 15. When the data is read, the high-voltage applying pad 21 is isolated from the bit line 19 without exerting influence upon the read out operation.