Patents by Inventor Shigeharu Okaji

Shigeharu Okaji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10008584
    Abstract: The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: June 26, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeharu Okaji
  • Publication number: 20150024563
    Abstract: The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed.
    Type: Application
    Filed: August 8, 2014
    Publication date: January 22, 2015
    Inventor: Shigeharu OKAJI
  • Patent number: 8829604
    Abstract: The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeharu Okaji
  • Patent number: 8404433
    Abstract: In order to suppress variation of a resist pattern size caused by a temperature unevenness at a prebaking process, applying a resist of a positive type or a negative type on a base substrate, prebaking, exposing, post-exposure baking, and forming the resist to be a predetermined shape by developing the resist are carried out. The prebaking is carried out at a temperature equal to or more than a detachment starting temperature of a protective group of a base resin included in the resist in a case where the resist is the positive type. In a case where the resist is the negative type, the prebaking is carried out at a temperature equal to or more than a cross-linking starting temperature of a cross-linker in a base resin included in the resist.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: March 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeharu Okaji
  • Publication number: 20130001677
    Abstract: The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 3, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Shigeharu OKAJI
  • Patent number: 8318597
    Abstract: The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm2 or above; grinding a surface of the first Au bump; stripping the photoresist; and removing the seed film by dry-etching.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeharu Okaji
  • Publication number: 20100330796
    Abstract: The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm2 or above; grinding a surface of the first Au bump; stripping the photoresist; and removing the seed film by dry-etching.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 30, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Shigeharu Okaji
  • Publication number: 20100255421
    Abstract: In order to suppress variation of a resist pattern size caused by a temperature unevenness at a prebaking process, applying a resist of a positive type or a negative type on a base substrate, prebaking, exposing, post-exposure baking, and forming the resist to be a predetermined shape by developing the resist are carried out. The prebaking is carried out at a temperature equal to or more than a detachment starting temperature of a protective group of a base resin included in the resist in a case where the resist is the positive type. In a case where the resist is the negative type, the prebaking is carried out at a temperature equal to or more than a cross-linking starting temperature of a cross-linker in a base resin included in the resist.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 7, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Shigeharu Okaji