Patents by Inventor Shigehiko KATO

Shigehiko KATO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977099
    Abstract: A method for manufacturing a semiconductor device in which probes and the layout of the electrode pads of a test element group (TEG) are associated is provided. As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Thus, it is necessary to associate the probes and the layout of the electrode pad. According to the method, a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology is provided.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 7, 2024
    Assignee: Hitachi High-Tech Corporation
    Inventors: Tomohisa Ohtaki, Takayuki Mizuno, Ryo Hirano, Toru Fujimura, Shigehiko Kato, Yasuhiko Nara, Katsuo Ohki, Akira Kageyama, Masaaki Komori
  • Publication number: 20240077712
    Abstract: Provided is an efficient method for attaching a tissue section. In the invention, one of problems is solved by changing attachment conditions of the tissue section depending on an organ from which the tissue section is derived. A technique of achieving good adhesiveness between a microscope slide and a section by introducing unevenness on a front surface of the microscope slide using reactive ion etching as one of the attachment conditions is provided. Further, a technique of optimizing the attachment of the section using a machine learning technique or the like is provided.
    Type: Application
    Filed: October 16, 2019
    Publication date: March 7, 2024
    Inventors: Toru FUJIMURA, Takahito HASHIMOTO, Shigehiko KATO, Eiko NAKAZAWA, Masahiko AJIMA, Akira SAWAGUCHI
  • Patent number: 11709199
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: July 25, 2023
    Assignee: Hitachi High-Tech Corporation
    Inventors: Tomohisa Ohtaki, Takayuki Mizuno, Ryo Hirano, Toru Fujimura, Shigehiko Kato, Yasuhiko Nara, Katsuo Ohki, Akira Kageyama, Masaaki Komori
  • Patent number: 11391756
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: July 19, 2022
    Assignee: Hitachi High-Tech Corporation
    Inventors: Ryo Hirano, Takayuki Mizuno, Tomohisa Ohtaki, Toru Fujimura, Shigehiko Kato, Yasuhiko Nara, Katsuo Ohki, Akira Kageyama, Masaaki Komori
  • Publication number: 20210048450
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to a method for manufacturing a semiconductor device of the present invention, the above-described problems can be solved by providing a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: February 18, 2021
    Inventors: Tomohisa OHTAKI, Takayuki MIZUNO, Ryo HIRANO, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Publication number: 20210033642
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: February 4, 2021
    Inventors: Ryo HIRANO, Takayuki MIZUNO, Tomohisa OHTAKI, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Publication number: 20210025936
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: January 28, 2021
    Inventors: Tomohisa OHTAKI, Takayuki MIZUNO, Ryo HIRANO, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI