Patents by Inventor Shigehiro Asano
Shigehiro Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10366003Abstract: According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed.Type: GrantFiled: July 20, 2016Date of Patent: July 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuhiro Fukutomi, Shinichi Kanno, Shigehiro Asano
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Publication number: 20190220197Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Applicant: Toshiba Memory CorporationInventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
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Publication number: 20190179745Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.Type: ApplicationFiled: January 23, 2019Publication date: June 13, 2019Applicant: Toshiba Memory CorporationInventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
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Patent number: 10248317Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: June 8, 2017Date of Patent: April 2, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 10229053Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.Type: GrantFiled: February 21, 2018Date of Patent: March 12, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
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Publication number: 20180260334Abstract: A data storage device capable of namespace re-sizing comprises a nonvolatile semiconductor storage device containing data accessed via a logical address that includes a namespace identifier and a logical block address, and a controller. The storage device can convert the namespace identifier to a base address using a first look up table. The storage device can further convert the logical block address to namespace allocation units of storage. The storage device can also determine a pointer using the base address, the namespace allocation units, and a second look up table. Further, the storage device can determine a full logical cluster address using the pointer.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Inventors: Shigehiro Asano, Julien Margetts, Philip David Rose
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Publication number: 20180239698Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.Type: ApplicationFiled: February 21, 2018Publication date: August 23, 2018Applicant: Toshiba Memory CorporationInventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
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Publication number: 20180203615Abstract: According to one embodiment, a storage control device has, as a unit of storage, a stripe including one or more chunks being storage areas included in any of a plurality of storages. The storage control device includes a first selector, a divider, and a determiner. The first selector is configured to select a stripe from a plurality of stripes on the basis of the number of one or more pieces of valid first data included in the stripe. The divider is configured to divide the chunk included in the stripe selected by the first selector into a plurality of partial chunks. The determiner is configured to determine the partial chunk that is to be a target of garbage collection on the basis of the number of one or more pieces of the valid first data included in the partial chunk.Type: ApplicationFiled: September 12, 2017Publication date: July 19, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yoshiki SAITO, Yohei HASEGAWA, Shohei ONISHI, Hidenori MATSUZAKI, Shigehiro ASANO
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Publication number: 20180143992Abstract: A storage system includes non-volatile storage devices and a control device. Each of the storage devices is divided into blocks, and data is erased in units of the blocks. The control device includes a setting unit and a writing/reading unit. The setting unit sets first storage regions obtained by dividing a storage region for each of the storage devices and sets second storage regions obtained by dividing storage regions of all of the storage devices for all of the storage devices. The writing/reading unit manages data stored in the storage devices in units of the second storage regions. The setting unit sets each of the first storage regions so that the first storage region for at least one of the plurality of storage devices includes the entirety of one or more blocks and sets each of the second storage regions to include two or more of the first storage regions.Type: ApplicationFiled: September 12, 2017Publication date: May 24, 2018Applicant: Toshiba Memory CorporationInventors: Yohei HASEGAWA, Yoshiki SAITO, Shohei ONISHI, Hidenori MATSUZAKI, Shigehiro ASANO
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Publication number: 20180129600Abstract: A memory system includes a nonvolatile memory having memory dies controlled in parallel and each including a plurality of physical blocks, and a controller. The controller manages a plurality of logical areas for storing data portions received from the host and parities calculated from the data portions, the logical areas including first and second logical areas for storing first and second parity groups, respectively. Each first parity group includes k data portions received from the host and m parities calculated therefrom. Each second parity group includes k? data portions received from the host and m? parities calculated therefrom. Also, the controller maps each logical area to storage locations in the non-volatile memory dies such that the data portions and the parities of any one parity group are each stored in a different physical block in a set of physical blocks selected from different non-volatile memory dies.Type: ApplicationFiled: November 2, 2017Publication date: May 10, 2018Inventors: Masahiro ISHIYAMA, Shigehiro ASANO
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Patent number: 9940233Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.Type: GrantFiled: December 8, 2016Date of Patent: April 10, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
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Publication number: 20170269843Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: June 8, 2017Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: HIROKUNI YANO, SHINICHI KANNO, TOSHIKATSU HIDA, HIDENORI MATSUZAKI, KAZUYA KITSUNAI, SHIGEHIRO ASANO
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Patent number: 9703486Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: August 10, 2015Date of Patent: July 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 9690691Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.Type: GrantFiled: July 2, 2013Date of Patent: June 27, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
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Publication number: 20170103017Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.Type: ApplicationFiled: December 8, 2016Publication date: April 13, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
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Patent number: 9569355Abstract: According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory.Type: GrantFiled: August 14, 2014Date of Patent: February 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yohei Hasegawa, Shigehiro Asano, Tokumasa Hara
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Publication number: 20170004070Abstract: According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed.Type: ApplicationFiled: July 20, 2016Publication date: January 5, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro FUKUTOMI, Shinichi KANNO, Shigehiro ASANO
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Publication number: 20160266827Abstract: A memory controller that controls data transfer performed between a memory device and another memory device, the memory controller includes: an acquiring unit that acquires command information which contains first address information indicating a first memory area to be accessed during the data transfer; a determining unit that determines whether the first memory area belongs to a specific external address space which represents a specific address space in an external memory; and a converting unit that, when the first memory area belongs to the specific external address space, converts, based on conversion information indicating correspondence relationship between the specific external address space and a specific internal address space which represents a specific address space in the first memory device, the first address information into second address information indicating a second memory area belonging to the specific internal address space.Type: ApplicationFiled: October 26, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yohei HASEGAWA, Yoshiki SAITO, Shigehiro ASANO
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Patent number: 9324653Abstract: On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.Type: GrantFiled: November 20, 2013Date of Patent: April 26, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Shinichi Kanno, Junji Yano
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Publication number: 20160015952Abstract: The present invention provides a microneedle patch which can solve the problem that microneedle production is difficult and requires high accuracy, the problem that time and mental burdens on a health professional and a patient are large, and the problem caused by compounding a plurality of drugs. The microneedle patch comprises a large number of drug-carrying microprojections 4 erected on one support sheet, each microprojection 4 having a drug layer 5 soluble in vivo at its top part and having an intermediate layer 6 under the drug layer 5, the intermediate layer 6 containing a polymeric substance for adhesion of the drug layer 5 to the support sheet, the drug layer 5 at the top part of the microprojection 4 containing a single drug, the microprojections 4 holding difference types of drugs being arranged together on the support sheet 2.Type: ApplicationFiled: March 11, 2014Publication date: January 21, 2016Applicant: TAKEDA PHARMACEUTICAL COMPANY LIMITEDInventors: Yoshihiro OMACHI, Yasuhiro HIRAISHI, Masami KUSAKA, Shigehiro ASANO, Masao NAGAO