Patents by Inventor Shigehiro Kuge
Shigehiro Kuge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7365578Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: July 3, 2007Date of Patent: April 29, 2008Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20070285146Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: July 3, 2007Publication date: December 13, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7268612Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: January 30, 2007Date of Patent: September 11, 2007Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20070120592Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: January 30, 2007Publication date: May 31, 2007Applicant: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7180362Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: September 15, 2004Date of Patent: February 20, 2007Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7157773Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.Type: GrantFiled: December 30, 2002Date of Patent: January 2, 2007Assignee: Renesas Technology Corp.Inventors: Hiroshi Kato, Shigehiro Kuge, Hideyuki Noda, Fukashi Morishita, Shuichi Ueno
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Patent number: 6962827Abstract: A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.Type: GrantFiled: August 14, 2003Date of Patent: November 8, 2005Assignee: Renesas Technology Corp.Inventors: Katsuya Furue, Shigeru Kikuda, Kiyohiro Furutani, Tetsushi Tanizaki, Shigehiro Kuge, Takashi Kono
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Patent number: 6897523Abstract: A semiconductor device is provided which includes a diode formed of a MISFET and having a current-voltage characteristic close to that of an ideal diode. Negatively charged particles (e.g. electrons: 8a) are trapped on the drain region (2) side of a silicon nitride film (4b) sandwiched between films of silicon oxide (4a, 4c). When a bias voltage is applied between the drain and source with the negatively charged particles (8a) thus trapped and in-channel charged particles (9a) induced by them, the MISFET exhibits different threshold values for channel formation depending on whether it is a forward bias or a reverse bias. That is to say, when a reverse bias is applied, the channel forms insufficiently and the source-drain current is less likely to flow, while the channel forms sufficiently and a large source-drain current flows when a forward bias is applied. This offers a current-voltage characteristic close to that of the ideal diode.Type: GrantFiled: August 5, 2002Date of Patent: May 24, 2005Assignee: Renesas Technology Corp.Inventors: Shuichi Ueno, Haruo Furuta, Shigehiro Kuge, Hiroshi Kato
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Publication number: 20050057288Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: September 15, 2004Publication date: March 17, 2005Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 6850454Abstract: Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.Type: GrantFiled: July 25, 2003Date of Patent: February 1, 2005Assignee: Renesas Technology Corp.Inventors: Shigehiro Kuge, Takeshi Hamamoto
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Patent number: 6809975Abstract: This DDR SDRAM includes a test mode entry signal generation circuit which sets a test mode entry signal at “H” level in accordance with a consecutive input of a first command, a second command, a test mode entry set command, a third command and a test mode register set command synchronously with a rising edge of a clock signal. This enables the DDR SDRAM to enter a test mode without using a high voltage. The DDR SDRAM can, therefore, enter the test mode even if it is incorporated into a registered DIMM.Type: GrantFiled: October 22, 2002Date of Patent: October 26, 2004Assignee: Renesas Technology Corp.Inventors: Shigeru Yamaoka, Shigehiro Kuge
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Patent number: 6781900Abstract: The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.Type: GrantFiled: September 5, 2002Date of Patent: August 24, 2004Assignee: Renesas Technology Corp.Inventors: Kiyohiro Furutani, Takeshi Hamamoto, Takashi Kubo, Shigehiro Kuge
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Patent number: 6777976Abstract: An output drive circuit is constructed by an output driving MOS transistor driving an output node in accordance with an internal read data, a termination controlling P-channel MOS transistor selectively rendered conductive in accordance with the internal read data when the output driving MOS transistor is non-conductive, and a P-channel MOS transistor rendered conductive to pull up the output node to a power supply voltage level at least when the output drive circuit is inactive. Data transfer is executed in an open drain manner, and the P-channel MOS transistor is utilized as a transistor for termination bus line. Data/signal is transferred fast in an active termination scheme with low current consumption, and an area occupied by the output drive circuit is reduced.Type: GrantFiled: September 18, 2002Date of Patent: August 17, 2004Assignee: Renesas Technology Corp.Inventor: Shigehiro Kuge
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Publication number: 20040145959Abstract: Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.Type: ApplicationFiled: July 25, 2003Publication date: July 29, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Shigehiro Kuge, Takeshi Hamamoto
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Patent number: 6731535Abstract: A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.Type: GrantFiled: June 6, 2003Date of Patent: May 4, 2004Assignee: Renesas Technology Corp.Inventors: Tsukasa Ooishi, Shuichi Ueno, Shigehiro Kuge
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Patent number: 6715096Abstract: An interface unit includes a timing control circuit for extracting an effective data window by detecting a point of change in a transferred data, and determining strobe timing for taking in the data in accordance with the extracted effective window; and a strobe clock generating circuit for generating a strobe clock signal for taking in the data under control of the timing control circuit. Regardless of the system structure, accurate data transfer is achieved between any semiconductor devices in the system.Type: GrantFiled: December 28, 2000Date of Patent: March 30, 2004Assignee: Renesas Technology Corp.Inventor: Shigehiro Kuge
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Publication number: 20040007734Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.Type: ApplicationFiled: December 30, 2002Publication date: January 15, 2004Inventors: Hiroshi Kato, Shigehiro Kuge, Hideyuki Noda, Fukashi Morishita, Shuichi Ueno
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Publication number: 20030202409Abstract: This DDR SDRAM includes a test mode entry signal generation circuit which sets a test mode entry signal at “H” level in accordance with a consecutive input of a first command, a second command, a test mode entry set command, a third command and a test mode register set command synchronously with a rising edge of a clock signal. This enables the DDR SDRAM to enter a test mode without using a high voltage. The DDR SDRAM can, therefore, enter the test mode even if it is incorporated into a registered DIMM.Type: ApplicationFiled: October 22, 2002Publication date: October 30, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shigeru Yamaoka, Shigehiro Kuge
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Publication number: 20030184343Abstract: An output drive circuit is constructed by an output driving MOS transistor driving an output node in accordance with an internal read data, a termination controlling P-channel MOS transistor selectively rendered conductive in accordance with the internal read data when the output driving MOS transistor is non-conductive, and a P-channel MOS transistor rendered conductive to pull up the output node to a power supply voltage level at least when the output drive circuit is inactive. Data transfer is executed in an open drain manner, and the P-channel MOS transistor is utilized as a transistor for termination bus line. Data/signal is transferred fast in an active termination scheme with low current consumption, and an area occupied by the output drive circuit is reduced.Type: ApplicationFiled: September 18, 2002Publication date: October 2, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Shigehiro Kuge
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Publication number: 20030174566Abstract: The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.Type: ApplicationFiled: September 5, 2002Publication date: September 18, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Kiyohiro Furutani, Takeshi Hamamoto, Takashi Kubo, Shigehiro Kuge