Abstract: A display scrolling circuit is provided which can give a variety to a display image by scrolling the display image for every display line without provision of a burden on a processor for computing a game. A game system to which the present invention is applied has a CPU 10, a video RAM (VRAM) 12, a character generator (CG) 14, scroll registers (SR) 16, 18, 20 and 22, a VRAM address control circuit 30, a CG address control circuit 32, an in-character transverse correction circuit 34 and a color palette 36. The VRAM 12 stores vertical and horizontal position data for every display line and absolute flags AF indicating whether these vertical and horizontal position data are absolute or relative values. The VRAM address control circuit 30 reads the position and other data from the VRAM 12 during the horizontal blanking period to set the read addresses of the VRAM 12 required to display one line. Therefore, the amount of scrolling for every display line can be set without provision of a burden on the CPU 10.

Abstract: The invention provides an object display system for calculating a set of object data including object identification data, vertical display position data and horizontal display position data for each of objects to be displayed and displaying the image of that object on a raster display, based on the calculated object data, the object display system having a shape generator pre-registered with the image of each object as block information represented by binary pixel data which are representative of transparent and opaque sections of the image, said shape generator being adapted to output the binary pixel data corresponding to one horizontal scan in the block of the object as transparent or opaque data for each pixel. By the shape generator judging whether each of pixels is transparent or opaque, the system can have very decreased amount of data required to perform the judgement and be of the entire simplified structure with decreased cost. Furthermore, the above judgement can be performed more rapidly.

Abstract: A circuit for sorting a plurality of inputted (reference-axis) data includes an index generator for generating an index (datum number) for each of the inputted data; a first buffer memory having storage areas each of which can be addressed by the data, the first buffer memory for storing an index generated by the index generator when the corresponding data is initially inputted into the index generator; a last buffer memory having storage areas each of which can be addressed by the data, the last buffer memory for updating and storing an index generated by the index generator at each time when the corresponding data is inputted thereinto; a chain buffer memory having chain index storage areas each of which can be addressed by the previous index in the chain; a first control for writing a new updated index into a chain index storage area addressed by a before-updated index at each time when the index of the last buffer memory is updated; a second control for writing the index of the data into the chain datum n

Abstract: An integrated circuit using, at least in its input end, a CMOS IC. This CMOS-input-type IC comprises an input terminal to which a signal is to be inputted, a switching signal terminal to which a switching signal for shifting from a main power source to a backup power source is to be inputted, and clamping means disposed between the input terminal and remaining parts of the CMOS-input-type-IC. The clamping means comprises an output buffer circuit which forcibly lowers or raises the signal, which is to be inputted to said input terminal, to a low level or a high level, respectively, when the switching signal is inputted to said switching signal terminal. With this clamping means, it is possible to prevent, for a long time, a rush current from generating in the CMOS-input-type IC when the power source is switched from the main power source to the backup power source, thus preventing the supply voltage from lowering.

Abstract: An object image indicating apparatus which reads out coordinate picture element information of the object from an object image memory in which object images are stored as coordinate picture element information in the vertical or horizontal direction and raster image-indicates on a CRT, includes a scale-up or scale-down circuit which scales up or down the coordinate picture element information read out of the object image memory to either one of the vertical or horizontal direction at least at a certain established scale factor, whereby the object can be indicated on the CRT at the scale factor to either one of the vertical or horizontal direction at least, and especially, a plurality of the objects can be continuously image-indicated on the CRT with scale-up or scale-down at requested scale factors.