Abstract: A synchronization control apparatus is included in an arithmetic processing device. The arithmetic processing device is connected to another arithmetic processing device via a data transfer device. The synchronization control apparatus is connected to a clock divider which divides an input clock signal into N. In the synchronization control apparatus: a detecting unit detects the rising or the falling of a divided clock signal; a monitoring unit monitors the elapsed time since the rising or the falling of the divided clock signal; a clock generating unit generates a control clock by multiplying the divided clock signal by N; a synchronization request receiving unit receives a synchronization request from the other arithmetic processing device; a clock control unit outputs the control clock; a synchronization request sending unit sends a synchronization request to the other arithmetic processing device via the data transfer device.

Abstract: A data storage control apparatus and method for reduction of traffic of an interconnect occurring in the timing of a cache miss within a CPU. The apparatus and method are realized by utilizing, as a response to the read request from the CPU, data tags DTAGs used for management of data registered to the cache memory within the CPU under the control of a local node and a retention tag used for holding secondary data indicating that the object data is not held in the cache memory of any CPU of a local node.

Abstract: A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache, includes a consumption determining unit that monitors a consumption status of a hardware resource used in the speculative fetch, and determines whether a consumption of the hardware resource exceeds a predetermined value; and a speculative-fetch issuing unit that stops issuing the speculative fetch when the consumption determining unit determines that the consumption of the hardware resource exceeds the predetermined value.

Abstract: A path selecting unit searches, upon receiving an enquiry of a path to an input/output device from a central processing unit, a storing unit that stores therein device identification information and path identification information by using device identification information included in the enquiry as a key, retrieves path identification information of an enquired path, and returns retrieved path identification information to the central processing unit in response to the enquiry. When one of the paths becomes unavailable, an updating unit updates the storing unit such that an unavailable path is not selected by the path selecting unit.

Abstract: A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data from among the data stored based on a predetermined priority, extract the desired data from a corresponding register, and outputs the desired data to the output unit; a detecting unit that detects an error in the desired data; a diagnostic-data writing unit that writes diagnostic data for diagnosing failure of the register in the register from which the desired data is extracted; and a diagnostic-data error detecting unit that detects an error in the diagnostic data.

Abstract: A data storage control apparatus and method for reduction of traffic of an interconnect occurring in the timing of a cache miss within a CPU. The apparatus and method are realized by utilizing, as a response to the read request from the CPU, data tags DTAGs used for management of data registered to the cache memory within the CPU under the control of a local node and a retention tag used for holding secondary data indicating that the object data is not held in the cache memory of any CPU of a local node.

Abstract: A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache, includes a consumption determining unit that monitors a consumption status of a hardware resource used in the speculative fetch, and determines whether a consumption of the hardware resource exceeds a predetermined value; and a speculative-fetch issuing unit that stops issuing the speculative fetch when the consumption determining unit determines that the consumption of the hardware resource exceeds the predetermined value.

Abstract: A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data from among the data stored based on a predetermined priority, extract the desired data from a corresponding register, and outputs the desired data to the output unit; a detecting unit that detects an error in the desired data; a diagnostic-data writing unit that writes diagnostic data for diagnosing failure of the register in the register from which the desired data is extracted; and a diagnostic-data error detecting unit that detects an error in the diagnostic data.