Abstract: Instruction-execution processors each execute a first instruction. A control processor converts a second instruction to be emulated into the first instruction, and enters the converted first instruction into the instruction-execution processors. In a parallel-execution period, each instruction-execution processor executes a writing-access instruction or a reading-access instruction to a memory, suspends writing of data into the memory caused by the writing-access instruction, and retains an execution history of the writing-access instruction and the reading-access instruction.

Abstract: Instruction-execution processors each execute a first instruction. A control processor converts a second instruction to be emulated into the first instruction, and enters the converted first instruction into the instruction-execution processors. In a parallel-execution period, each instruction-execution processor executes a writing-access instruction or a reading-access instruction to a memory, suspends writing of data into the memory caused by the writing-access instruction, and retains an execution history of the writing-access instruction and the reading-access instruction.

Abstract: A technique realizes execution of various combinations of arithmetic operations in, for example, SIMD floating-point multiply-add arithmetic operation, with less instruction kind codes. An arithmetic operating apparatus sets, in one or more unused bits of a single arithmetic instruction, particular instruction information to instruct at least one of arithmetic operators to perform a process different from an ordinary process.

Abstract: An information processing device includes a plurality of barrier banks, and one or more processors including at least one of the plurality of barrier banks. Each of barrier banks includes one or more hardware threads and a barrier synchronization mechanism. The barrier synchronization mechanism includes a bottom unit having a barrier state, and a bitmap indicating that each of the one or more hardware threads has arrived at a synchronization point, and a top unit having a non-arrival counter indicating the number of barrier banks yet to be synchronized. The bottom unit notifies of bottom unit synchronization completion when all the one or more hardware threads have arrived at a barrier synchronization point. The non-arrival counter decrements its value by 1 upon receipt of the bottom unit synchronization completion, and the top unit sets the barrier state to a value indicating synchronization completion when the non-arrival counter decrements to 0.

Abstract: A data compression apparatus includes a memory and a processor. The processor extracts a second character string as a matching string from a character string after a first character string in a character string of data before compression that is stored in the memory, the second character string being identical with the first character string, and identifies a length of the matching string, and a relative position indicating how many addresses the first character string precedes the second character string by. The processor extracts a third character string having a length that is less than the relative position from the extracted second character string. The processor encodes a length of the third character string. The processor encodes the relative position.

Abstract: A data compression apparatus includes a memory and a processor. The processor extracts a second character string as a matching string from a character string after a first character string in a character string of data before compression that is stored in the memory, the second character string being identical with the first character string, and identifies a length of the matching string, and a relative position indicating how many addresses the first character string precedes the second character string by. The processor extracts a third character string having a length that is less than the relative position from the extracted second character string. The processor encodes a length of the third character string. The processor encodes the relative position.

Abstract: An information processing device includes a plurality of barrier banks, and one or more processors including at least one of the plurality of barrier banks. Each of barrier banks includes one or more hardware threads and a barrier synchronization mechanism. The barrier synchronization mechanism includes a bottom unit having a barrier state, and a bitmap indicating that each of the one or more hardware threads has arrived at a synchronization point, and a top unit having a non-arrival counter indicating the number of barrier banks yet to be synchronized. The bottom unit notifies of bottom unit synchronization completion when all the one or more hardware threads have arrived at a barrier synchronization point. The non-arrival counter decrements its value by 1 upon receipt of the bottom unit synchronization completion, and the top unit sets the barrier state to a value indicating synchronization completion when the non-arrival counter decrements to 0.

Abstract: An information processing device includes a plurality of barrier banks, and one or more processors including at least one of the plurality of barrier banks. Each of barrier banks includes one or more hardware threads and a barrier synchronization mechanism. The barrier synchronization mechanism includes a bottom unit having a barrier state, and a bitmap indicating that each of the one or more hardware threads has arrived at a synchronization point, and a top unit having a non-arrival counter indicating the number of barrier banks yet to be synchronized. The bottom unit notifies of bottom unit synchronization completion when all the one or more hardware threads have arrived at a barrier synchronization point. The non-arrival counter decrements its value by 1 upon receipt of the bottom unit synchronization completion, and the top unit sets the barrier state to a value indicating synchronization completion when the non-arrival counter decrements to 0.

Abstract: In a data compression apparatus, a search unit examines the sequence of symbols in compression target data, and searches for a second symbol string having the same sequence of symbols as a first symbol string that occurred previously, and a code generation unit encodes the second symbol string into a code containing information that specifies a block to which the beginning of the first symbol string belongs. In a data decompression apparatus, a code acquisition unit sequentially acquires codes from the beginning of the compressed data, and when the code of the second symbol string is acquired, a decompression unit acquires, from a storage device, one or more blocks starting with a block to which the beginning of the decompressed first symbol string belongs, on the basis of the information contained in the acquired code, and decompresses the second symbol string.

Abstract: An information processing device includes a plurality of barrier banks, and one or more processors including at least one of the plurality of barrier banks. Each of barrier banks includes one or more hardware threads and a barrier synchronization mechanism. The barrier synchronization mechanism includes a bottom unit having a barrier state, and a bitmap indicating that each of the one or more hardware threads has arrived at a synchronization point, and a top unit having a non-arrival counter indicating the number of barrier banks yet to be synchronized. The bottom unit notifies of bottom unit synchronization completion when all the one or more hardware threads have arrived at a barrier synchronization point. The non-arrival counter decrements its value by 1 upon receipt of the bottom unit synchronization completion, and the top unit sets the barrier state to a value indicating synchronization completion when the non-arrival counter decrements to 0.

Abstract: A technique realizes execution of various combinations of arithmetic operations in, for example SIMD floating-point multiply-add arithmetic operation, with less instruction kind codes. An arithmetic operating apparatus includes a setting unit that sets in one or more unused bits of a single instruction extended instruction information to instruct at least one of a register and arithmetic operators to perform an extended process different from an ordinary process.

Abstract: A method and an apparatus for cutting a wafer from a crystalline ingot, by directing a stream or streams of etching gas at the crystalline ingot in a vacuum. Waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.

Abstract: A method and an apparatus for producing a wafer from a crystalline ingot, wherein the method supplies an etching gas, having a high etching property for at least one constituent of the crystalline ingot, in a state of a molecular beam stream on a predetermined part of the crystalline ingot to be processed, volatilizing the predetermined part gradually from the ingot, and then removing the predetermined part entirely so as to cut the wafer from the ingot. According to the method, waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.

Abstract: Pharmaceutically useful compounds are 2,5,6,7-tetranor-4,8-inter-m-phenylene PGI.sub.2 derivatives which are excellently stable and potent in vivo.