Patents by Inventor Shigeki Kamio

Shigeki Kamio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable logic device using a two bit security scheme to prevent unauthorized access
    Patent number: 6076149
    Abstract: For a data processing device having a main memory comprised of a non-volatile memory and a CPU, memory protection and security are ensured for its programs and so forth. An auxiliary memory for storing security bit data is provided, for example, in an EPROM that comprises the main memory. Assuming that the result read by the CPU is "0" when a current flows between a drain and a source of a transistor in the EPROM, and "1" when the current does not flow, then the security bit data read from two transistors A and B are A=1 and B=1, which means they are set so that access to the main memory and a write to the auxiliary memory are prohibited. With A=0 and B=0, security is set, but a write to the auxiliary memory is permitted; with A=1 (0) and B=0 (1), security is reset.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: June 13, 2000
    Assignee: Motorola, Inc.
    Inventors: Tadashi Usami, Hideki Kondo, Shigeki Kamio