Patents by Inventor Shigeki Koya

Shigeki Koya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200052663
    Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 13, 2020
    Inventors: Shigeki KOYA, Yasunari UMEMOTO, Yuichi SAITO, Isao OBU, Takayuki TSUTSUI
  • Publication number: 20200027876
    Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 23, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Shigeki KOYA, Yasunari UMEMOTO, Takayuki TSUTSUI
  • Patent number: 10541320
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: January 21, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Publication number: 20200006536
    Abstract: A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Kingo KUROTANI, Takashi KITAHARA, Shigeki KOYA
  • Patent number: 10523161
    Abstract: A power amplification module includes: an amplifier that amplifies an input signal and outputs an amplified signal; and a harmonic-termination circuit to which harmonics of the amplified signal are input and the impedance of which is controlled in accordance with the frequency of a harmonic. The power amplification module can operate in a first mode in which a power supply voltage changes in accordance with the average voltage value of the amplified signal over a prescribed time period or in a second mode in which the power supply voltage changes in accordance with the envelope of the input signal. The impedance of the harmonic-termination circuit is controlled such that at least one even-ordered harmonic is short-circuited when the power amplification module operates in the first mode and at least one odd-ordered harmonic of third order or higher is short-circuited when the power amplification module operates in the second mode.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 31, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shigeki Koya
  • Publication number: 20190386122
    Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Isao OBU, Kaoru IDENO, Shigeki KOYA
  • Patent number: 10374071
    Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, an emitter layer, and a semiconductor layer that are laminated in this order, wherein the emitter layer includes a first region having an upper surface on which the semiconductor layer is laminated, and a second region being adjacent to the first region and having an upper surface that is exposed, and the first and second regions of the emitter layer have higher doping concentrations in portions near the upper surfaces than in portions near an interface between the emitter layer and the base layer.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 6, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunari Umemoto, Shigeki Koya, Shigeru Yoshida, Isao Obu
  • Publication number: 20190237566
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Application
    Filed: April 4, 2019
    Publication date: August 1, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Publication number: 20190214382
    Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 11, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki KOYA, Takayuki TSUTSUI, Kazuhito NAKAI, Yusuke TANAKA
  • Publication number: 20190172933
    Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 6, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Publication number: 20190158039
    Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Inventors: Shigeki Koya, Takayuki Tsutsui, Yasunari Umemoto, Isao Obu, Satoshi Tanaka
  • Patent number: 10297680
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 21, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Publication number: 20190115457
    Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 18, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
  • Publication number: 20190088768
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 21, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Publication number: 20180331208
    Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
  • Publication number: 20180287571
    Abstract: A power amplification module includes: an amplifier that amplifies an input signal and outputs an amplified signal; and a harmonic-termination circuit to which harmonics of the amplified signal are input and the impedance of which is controlled in accordance with the frequency of a harmonic. The power amplification module can operate in a first mode in which a power supply voltage changes in accordance with the average voltage value of the amplified signal over a prescribed time period or in a second mode in which the power supply voltage changes in accordance with the envelope of the input signal. The impedance of the harmonic-termination circuit is controlled such that at least one even-ordered harmonic is short-circuited when the power amplification module operates in the first mode and at least one odd-ordered harmonic of third order or higher is short-circuited when the power amplification module operates in the second mode.
    Type: Application
    Filed: June 1, 2018
    Publication date: October 4, 2018
    Inventor: Shigeki KOYA
  • Publication number: 20180248023
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 30, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Publication number: 20180240899
    Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 23, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
  • Patent number: 10056476
    Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: August 21, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
  • Patent number: 10014832
    Abstract: A power amplification module includes: an amplifier that amplifies an input signal and outputs an amplified signal; and a harmonic-termination circuit to which harmonics of the amplified signal are input and the impedance of which is controlled in accordance with the frequency of a harmonic. The power amplification module can operate in a first mode in which a power supply voltage changes in accordance with the average voltage value of the amplified signal over a prescribed time period or in a second mode in which the power supply voltage changes in accordance with the envelope of the input signal. The impedance of the harmonic-termination circuit is controlled such that at least one even-ordered harmonic is short-circuited when the power amplification module operates in the first mode and at least one odd-ordered harmonic of third order or higher is short-circuited when the power amplification module operates in the second mode.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 3, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shigeki Koya