Patents by Inventor Shigeki Otsuka

Shigeki Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150043752
    Abstract: An audio signal output device (1) includes an audio signal output portion (15), a volume setting information acquisition portion (15), and a control portion (10). The control portion is configured to calculate the output volume of an external device on the basis of volume information of content and volume setting information of the external device and perform control of lowering the output volume of the external device in the case where the output volume is higher than a prescribed volume threshold.
    Type: Application
    Filed: March 29, 2013
    Publication date: February 12, 2015
    Inventors: Yuichi Ito, Atsushi Taniguchi, Shigeki Otsuka, Kota Hirai, Takashi Fujii
  • Patent number: 8766408
    Abstract: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takashi Noma, Shigeki Otsuka, Yuichi Morita, Kazuo Okada, Hiroshi Yamada, Katsuhiko Kitagawa, Noboru Okubo, Shinzo Ishibe, Hiroyuki Shinogi
  • Publication number: 20130259265
    Abstract: This audio signal output device includes an audio signal output portion, a volume setting information acquisition portion, and a control portion acquiring maximum volume information of volume information of an audio signal of content. The control portion is configured to calculate the maximum output volume of an external device on the basis of the maximum volume information of the content and volume setting information of the external device and perform control of lowering the output volume of the external device when the maximum output volume is higher than a prescribed volume threshold.
    Type: Application
    Filed: February 26, 2013
    Publication date: October 3, 2013
    Applicant: Funai Electric Co., Ltd.
    Inventors: Atushi TANIGUCHI, Shigeki Otsuka, Kota Hirai, Yuichi Ito, Takashi Fujii
  • Patent number: 8035215
    Abstract: The invention is directed to prevent corrosion of a semiconductor device. In the semiconductor device manufacturing method of the invention, a semiconductor substrate is etched from its back surface in a position corresponding to a first wiring formed on the semiconductor substrate with a first insulation film therebetween, to form a first opening exposing the first insulation film. Next, the insulation film exposed in the first opening is etched to form a second opening exposing the first wiring, and then the semiconductor substrate is etched to increase a diameter of the first opening and form a first opening having the larger diameter. Then, a second insulation film is formed on the back surface of the semiconductor substrate including on the first wiring through the first and second openings, and then the second insulation film covering the first wiring is etched.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 11, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hiroshi Kanamori, Shigeki Otsuka, Yuichi Morita, Akira Suzuki
  • Patent number: 8001507
    Abstract: A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: August 16, 2011
    Assignee: Funai Electric Co., Ltd.
    Inventor: Shigeki Otsuka
  • Patent number: 7986021
    Abstract: The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring formed on a back surface of a semiconductor substrate on an output image. A reflection layer is formed between a light receiving element and a wiring layer, that reflects an infrared ray toward a light receiving element the without transmitting it to the wiring layer, the infrared ray entering from a light transparent substrate toward the wiring layer through a semiconductor substrate. The reflection layer is formed at least in a region under the light receiving element uniformly or only under the light receiving element. Alternatively, an anti-reflection layer having a function of absorbing the entering infrared ray to prevent transmission thereof may be formed instead of the reflection layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: July 26, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Kazuo Okada, Katsuhiko Kitagawa, Takashi Noma, Shigeki Otsuka, Hiroshi Yamada, Shinzo Ishibe, Yuichi Morita, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
  • Patent number: 7981807
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 19, 2011
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Publication number: 20100240279
    Abstract: This present invention relates to a double-layered cup structure for an adhesively attachable strapless, backless bra comprising an exterior form and an interior pad that are both removable and replaceable
    Type: Application
    Filed: February 1, 2010
    Publication date: September 23, 2010
    Inventor: Shigeki Otsuka
  • Patent number: 7633133
    Abstract: This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is formed on a front surface of a semiconductor substrate, and a plurality of ball-shaped conductive terminals is disposed on a back surface of the semiconductor substrate. Each of the conductive terminals is electrically connected to a pad electrode on the front surface of the semiconductor substrate through a wiring layer. The wiring layer and the conductive terminal are formed on the back surface of the semiconductor substrate except in a region overlapping the light receiving element in a vertical direction, and are not disposed in a region overlapping the light receiving element.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: December 15, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Kazuo Okada, Shinzo Ishibe, Katsuhiko Kitagawa, Yuichi Morita, Shigeki Otsuka, Hiroshi Yamada, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
  • Publication number: 20090108893
    Abstract: A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 30, 2009
    Inventor: Shigeki Otsuka
  • Publication number: 20080171421
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Application
    Filed: March 19, 2008
    Publication date: July 17, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Akira SUZUKI, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Patent number: 7371693
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: May 13, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Publication number: 20070210437
    Abstract: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 13, 2007
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Shigeki Otsuka, Yuichi Morita, Kazuo Okada, Hiroshi Yamada, Katsuhiko Kitagawa, Noboru Okubo, Shinzo Ishibe, Hiroyuki Shinogi
  • Publication number: 20070145590
    Abstract: This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is formed on a front surface of a semiconductor substrate, and a plurality of ball-shaped conductive terminals is disposed on a back surface of the semiconductor substrate. Each of the conductive terminals is electrically connected to a pad electrode on the front surface of the semiconductor substrate through a wiring layer. The wiring layer and the conductive terminal are formed on the back surface of the semiconductor substrate except in a region overlapping the light receiving element in a vertical direction, and are not disposed in a region overlapping the light receiving element.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 28, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Takashi Noma, Kazuo Okada, Shinzo Ishibe, Katsuhiko Kitagawa, Yuichi Morita, Shigeki Otsuka, Hiroshi Yamada, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
  • Publication number: 20070145420
    Abstract: The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring formed on a back surface of a semiconductor substrate on an output image. A reflection layer is formed between a light receiving element and a wiring layer, that reflects an infrared ray toward a light receiving element the without transmitting it to the wiring layer, the infrared ray entering from a light transparent substrate toward the wiring layer through a semiconductor substrate. The reflection layer is formed at least in a region under the light receiving element uniformly or only under the light receiving element. Alternatively, an anti-reflection layer having a function of absorbing the entering infrared ray to prevent transmission thereof may be formed instead of the reflection layer.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 28, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kazuo Okada, Katsuhiko Kitagawa, Takashi Noma, Shigeki Otsuka, Hiroshi Yamada, Shinzo Ishibe, Yuichi Morita, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
  • Publication number: 20060180933
    Abstract: The invention is directed to prevent corrosion of a semiconductor device. In the semiconductor device manufacturing method of the invention, a semiconductor substrate is etched from its back surface in a position corresponding to a first wiring formed on the semiconductor substrate with a first insulation film therebetween, to form a first opening exposing the first insulation film. Next, the insulation film exposed in the first opening is etched to form a second opening exposing the first wiring, and then the semiconductor substrate is etched to increase a diameter of the first opening and form a first opening having the larger diameter. Then, a second insulation film is formed on the back surface of the semiconductor substrate including on the first wiring through the first and second openings, and then the second insulation film covering the first wiring is etched.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 17, 2006
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Hiroshi Kanamori, Shigeki Otsuka, Yuichi Morita, Akira Suzuki
  • Publication number: 20040229445
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Application
    Filed: February 24, 2004
    Publication date: November 18, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Patent number: 6632918
    Abstract: The object of the present invention is to provide a method of reclaiming crosslinked rubber, which can reclaim various kinds of crosslinked rubbers whose reclamation is difficult. The method of reclaiming crosslinked rubber 10 of the present invention includes a step of reclaiming crosslinked rubber by applying shear stress to the crosslinked rubber 10, wherein the maximum pressure in the reclaiming step is 1.5 MPa or more.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: October 14, 2003
    Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyoda Gosei Co., Ltd., Toyota Jidosha Kabushiki Kaisha
    Inventors: Mitsumasa Matsushita, Makoto Mouri, Hirotaka Okamoto, Kenzo Fukumori, Norio Sato, Masahito Fukuta, Hidenobu Honda, Katsumi Nakashima, Tamotsu Watanabe, Shigeki Otsuka, Masao Owaki