Abstract: The invention is to achieve highly precise voice recognition in efficient manner utilizing plural voice recognition apparatuses connected to a network. A communication terminal device executes voice recognition on the voice of the user, utilizing highly precise plural voice recognition apparatuses connected to a network. Then the communication terminal device compares the scores of the results of recognition obtained respectively from the voice recognition apparatuses and selects one of the results.

Abstract: An arrangement for executing a process in a data processing system using first and second programs each including executable codes and data in coordinated fashion in which a portion of the data and executable codes from the first program is provided to the second program during execution of the process. In execution of the process, portions of the data and executable codes provided by the first program to the second program are forcibly added or forcibly substituted and executed by the second program. The data and executable code portions are provided by injection and the injection and execution are conducted by imparting an acknowledgement of the addition or substitution and execution to the first program by the second program.

Abstract: In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state" when the data is shared with other cache memories, and is set to a "shared stale state" when the data in the "shared state" becomes stale by updating performed in another cache memory. Each processor monitors a transaction generated on a bus, derives a data portion from the bus when it is in the same address as the data in the "shared stale state" of its own cache memory, thereby updating the data in the address and making the state of the data a "shared state".

Abstract: According to a data management method of managing shared data which is shared by a plurality of processes and data inherent in a process which exists during execution of one particular process and disappears when the process is finished, when each process fetches shared data from a data base into a memory, whether the shared data requires data inherent in the process is checked. Any inherent data of the process is determined, if necessity for that data is determined. The determined inherent data of the process is stored in the memory. A pointer for the inherent data of the process, which is stored in the memory, is stored into the fetched shared data in accordance with attributes inherent in the process requiring the inherent data of the process.

Abstract: This disclosure relates to a terminal unit for processing voice information which is adopted in a network system for transmitting and receiving voice information. This disclosure also pertains to a group of such terminal units. In a case where a voice converter is not provided in the terminal unit or when the use of the voice converter is suppressed, the terminal unit converts received voice information into a medium other than voice, for example, into characters, and thereby conveys it to a receiver. In a case where the terminal unit which receives the voice information is not provided with the function of converting the received voice information into a medium other than voice, the terminal unit requests another terminal unit within the terminal unit group to convert the voice information into a medium other than voice and thereby conveys it to a receiver.

Abstract: In a multiprocessor system wherein a main storage is divided into a plurality of banks and a plurality of common buses are provided, in order to access the main storage. Each processor selects and acquires one of the buses in accordance with the utilization status of the common buses, and releases the bus after transmitting an access request utilizing the acquired bus. After processing the request, the main storage selects and acquires one of the buses in accordance with the utilization status of the common buses at that time independently of the bus which has transmitted the request, and transmits a result of the processing to the processor which has transmitted the access request utilizing the acquired bus.

Abstract: Disclosed is a relational algebra engine which has a sort engine, a merge engine, a control processor and a common bus. The sort engine has a plurality of first processing elements which are connected in series. Each first processing element includes first and second buffer memories, a first memory which has a FIFO function, and a first processor which sorts input data elements in accordance with a predetermined rule by using the first and second buffer memories and the first memory which has the FIFO function. The first and second buffer memories and the first memory which has the FIFO function are disposed in parallel. The merge engine has two second processing elements which are disposed in parallel.

Abstract: A data processing device applied to a computed tomography system which examines a living body utilizing radiation of X-rays is disclosed. The X-rays which have penetrated the living body are converted into electric signals in a detecting section. The electric signals are acquired and converted from an analog form into a digital form in a data acquisition section, and then supplied to a matrix data-generating section included in the data processing device. By this matrix data-generating section are generated matrix data which correspond to a plurality of projection data. These matrix data are supplied to a partial sum-producing section. The partial sums respectively corresponding to groups of the matrix data are calculated in this partial sum-producing section and then supplied to an accumulation section. In this accumulation section, the final value corresponding to the total sum of the matrix data is calculated, whereby the calculation for image reconstruction is performed.

Abstract: In a data processing system having a slave computer connecting to a host central processing unit and a host main memory, the slave computer has no internal random access memory and includes an arithmetic logic operating means. The arithmetic logic operating means calculates an address of the host main memory. A DMA interface directly makes an access to the host main memory to fetch operand data into the slave computer. The arithmetic logic operating means computes the operand data under control of a microprogram control section and directly loads the computed result to the host main memory through the DMA interface.

Abstract: A data processor used with a host computer is constructed by a plurality of memory units, at least one arithmetic and logic unit, a register file and a microprogram memory for storing microprograms to control these circuit components. The first field of each microinstruction of the microprogram is supplied to a first logic converting circuit of which the output signal drives each memory unit. The third field of the microinstruction is supplied to the second logic converting circuit of which the output signal causes the data stored in selected registers of the register file to be supplied to the arithmetic and logic unit. The arithmetic and logic unit operates upon the data supplied in accordance with the designation by the second field, and loads the result of the operation into the register specified by one of the outputs of the second logic converting circuit.

Abstract: Apparatus for calculating a plurality of interpolation values is adapted to calculate linear interpolation values, consisting of a second data train, from a first data train and includes a memory for storing the first data train and a calculator for calculating the interpolation value from the corresponding two data in the first data train read out of the memory.

Abstract: A matrix arithmetic apparatus which comprises a plurality of exclusive memories provided correspondingly to the respective items of a matrix or vector each including a plurality of elements in order to store element data corresponding to the elements. An arithmetic operation of Y=A.multidot.X+B is carried out with respect to the element data read out the memories wherein multiplication (A.multidot.X) and addition {(A.multidot.X)+B} of data representing the respective elements are undertaken by the exclusive arithmetic units by a pipe line system. Internal address computers corresponding to the memories are provided in order to determine a memory address of each of the memories from which a stored data is to be read out.