Patents by Inventor Shigeki Taira
Shigeki Taira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8918646Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.Type: GrantFiled: April 26, 2012Date of Patent: December 23, 2014Assignee: Renesas Electronics CorporationInventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
-
Patent number: 8407533Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.Type: GrantFiled: July 11, 2011Date of Patent: March 26, 2013Assignee: Hitachi, Ltd.Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
-
Patent number: 8356235Abstract: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations is restricted. To solve the above problems, the present invention records data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.Type: GrantFiled: September 29, 2009Date of Patent: January 15, 2013Assignee: Hitachi, Ltd.Inventors: Osamu Kawamae, Taku Hoshizawa, Harukazu Miyamoto, Shigeki Taira, Yukari Katayama
-
Publication number: 20120331186Abstract: The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.Type: ApplicationFiled: September 5, 2012Publication date: December 27, 2012Inventors: Yasushi NAGAI, Hiroshi NAKAGOE, Shigeki TAIRA
-
Patent number: 8266340Abstract: The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.Type: GrantFiled: April 2, 2012Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
-
Publication number: 20120210133Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
-
Publication number: 20120191882Abstract: The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.Type: ApplicationFiled: April 2, 2012Publication date: July 26, 2012Inventors: Yasushi NAGAI, Hiroshi Nakagoe, Shigeki Taira
-
Patent number: 8181024Abstract: In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.Type: GrantFiled: July 18, 2007Date of Patent: May 15, 2012Assignee: Renesas Electronics CorporationInventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
-
Patent number: 8176221Abstract: A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption.Type: GrantFiled: March 21, 2008Date of Patent: May 8, 2012Assignee: Renesas Electronics CorporationInventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
-
Publication number: 20110271154Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: Hitachi, Ltd.Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
-
Patent number: 7984340Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.Type: GrantFiled: July 25, 2008Date of Patent: July 19, 2011Assignee: Hitachi, Ltd.Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
-
Patent number: 7984339Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.Type: GrantFiled: July 25, 2008Date of Patent: July 19, 2011Assignee: Hitachi, Ltd.Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
-
Patent number: 7979753Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.Type: GrantFiled: July 25, 2008Date of Patent: July 12, 2011Assignee: Hitachi, Ltd.Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
-
Publication number: 20100306511Abstract: There is a need for providing a communication data processor easily adaptable to network configurations required for industrial Ethernet. The apparatus successively analyzes received packets. The apparatus uses a register to determine whether or not to transmit the received packet as transmission data to another port. Rewritable memory saves a program code that provides control for analyzing a reception packet and generating a transmission packet. The apparatus is capable of complying with various communication protocols by changing the program code.Type: ApplicationFiled: May 26, 2010Publication date: December 2, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Mochizuki, Takatoshi Kato, Nobuaki Kohinata, Shigeki Taira
-
Publication number: 20100257288Abstract: A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption.Type: ApplicationFiled: March 21, 2008Publication date: October 7, 2010Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
-
Publication number: 20100241771Abstract: A peripheral circuit with a host load adjusting function which is capable of readily carrying out control so that the amounts of data processed by the peripheral circuit and a host CPU are balanced by limiting interrupts made by the peripheral circuit, usage of a memory bus bandwidth, and a processing throughput of data. A typical embodiment of the present invention has an adjustment limitation setting unit setting a minimum value of an interval of interrupt requests generated by the peripheral circuit with the host load adjusting function, and a cycle counter counting generation timing of the interrupt requests, and compares a value of the cycle counter with the interval set in the adjustment limitation setting unit, thereby suppressing the interrupt requests generated at an interval shorter than the set interval.Type: ApplicationFiled: March 19, 2008Publication date: September 23, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasushi Nagai, Hiroshi Nakagoe, Shigeki Taira
-
Patent number: 7747910Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.Type: GrantFiled: July 25, 2008Date of Patent: June 29, 2010Assignee: Hitachi, Ltd.Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
-
Patent number: 7657817Abstract: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations is restricted. To solve the above problems, the present invention records data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.Type: GrantFiled: July 31, 2008Date of Patent: February 2, 2010Assignee: Hitachi, Ltd.Inventors: Osamu Kawamae, Taku Hoshizawa, Harukazu Miyamoto, Shigeki Taira, Yukari Katayama
-
Publication number: 20100017679Abstract: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations is restricted. To solve the above problems, the present invention records data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.Type: ApplicationFiled: September 29, 2009Publication date: January 21, 2010Applicant: HITACHI, LTDInventors: Osamu KAWAMAE, Taku Hoshizawa, Harukazu Miyamoto, Shigeki Taira, Yukari Katayama
-
Patent number: 7647542Abstract: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations is restricted. To solve the above problems, the present invention records data in a management area in units smaller than ordinary units for recorded data to suitably record information in a limited management area and thereby efficiently use the user data area. At that time, the present invention simplifies interleave processing usually applied to ordinary recorded data, and performs the simplified interleave processing on a data structure (for data of small size) of the present invention so as to ensure the signal processing compatibility between the ordinary data and data having the data structure according to the present invention.Type: GrantFiled: July 31, 2008Date of Patent: January 12, 2010Assignee: Hitachi, Ltd.Inventors: Osamu Kawamae, Taku Hoshizawa, Harukazu Miyamoto, Shigeki Taira, Yukari Katayama