Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: An equalizing filter circuit includes a first transmission line in which a plurality of first delay devices 104a are connected in cascade to input terminal 101, a second transmission line in which a plurality of second delay devices 107a are connected in cascade to output terminal 102, a plurality of weighting circuits 105a connected in parallel between the first transmission line and the second transmission line and having a gain which is adjustable by setting coefficients, and variable adjusting circuit 108a arranged at the output side of at least one of weighting circuits 105a for correcting a fluctuation of the output characteristics of the weighting circuits.

Abstract: A clock and data recovery circuit including a phase synchronization loop including an oscillator, the oscillation frequency of which is variably controlled, the phase synchronization loop performing phase-synchronization of a clock signal output from the oscillator with an input data signal. The circuit also includes a discriminator circuit, responsive to a clock signal for discrimination, for discriminating the input data signal and outputting the discriminated signal. The circuit further includes a phase detector circuit for detecting the phase difference between an output data signal, discriminated and output by the discriminator circuit, and the input data signal. The circuit also includes a phase shift circuit for shifting the phase of the clock signal, output from the oscillator, based on a comparison result output from the phase detector circuit. The clock signal, which is output from the phase shift circuit, is supplied as the clock signal for discrimination to the discriminator circuit.

Abstract: In an equalizing filter circuit having an input terminal 101, an output terminal 102, delay devices 104 connected in multi-stage to the input terminal 101, and a plurality of weighting circuits 105 which are branched from and connected to the plurality of delay devices to thereby combine respective output signals of the weighting circuits, gain adjustment of the weighting circuits is performed to determine a coefficient of the equalizing filter circuit without depending on a load connected to the output terminal. Thus, an amount of compensation for a distorted waveform may be enhanced. To this end, an impedance converting circuit 108 is connected between at least one weighting circuit and the output terminal.

Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: A voltage controlled oscillator of the present invention includes power supply terminal (101), control terminal (2) for controlling an output frequency, output terminals (3a, 3b), cross-coupled transistors (5a, 5b), capacitances (6a, 6b, 7a, 7b), LC tanks (10a, 10b), resistor (117), grounding capacitance (18) and center frequency control circuit (16). Center frequency control circuit (16) includes resistors (11a, 11b), grounding capacitance (12), center frequency control terminal (4) for controlling a center frequency of the output frequency, and voltage-divider circuit (15). Resistors (11a, 11b) are connected to the base terminals of cross-coupled transistors (5a, 5b), the other ends of resistors (11a, 11b) are connected to each other, and, to this connecting point, one end of grounding capacitance (12) and one end of voltage-divider circuit (15) are connected. The other end of voltage-divider circuit (15) is connected to center frequency control terminal (4).

Abstract: An equalizing filter circuit includes a first transmission line in which a plurality of first delay devices 104a are connected in cascade to input terminal 101, a second transmission line in which a plurality of second delay devices 107a are connected in cascade to output terminal 102, a plurality of weighting circuits 105a connected in parallel between the first transmission line and the second transmission line and having a gain which is adjustable by setting coefficients, and variable adjusting circuit 108a arranged at the output side of at least one of weighting circuits 105a for correcting a fluctuation of the output characteristics of the weighting circuits.

Abstract: An object of the present invention is to realize a compensation circuit which can cope with rapidly fluctuating polarization mode dispersion, and the configuration thereof is a polarization dispersion compensation circuit for compensating polarization mode dispersion which takes place when a signal propagates on a transmission path, characterized by comprising: a front-end compensation part configured as a transversal filter for shaping a waveform subjected to polarization mode dispersion; and a data tracking/recovery part including a PLL-type data recovery circuit having a loop frequency band higher than the fluctuation frequency of polarization mode dispersion, and that tracks the temporal fluctuation of the polarization mode dispersion to recover data.

Abstract: It is an object of the present invention to realize, in a coating and developing apparatus including an inspection section, reduction in the startup time, cost reduction, and an improved operating rate of the inspection section. In the present invention, a control program of the coating and developing apparatus is set such that a processing flow and an inspection flow can be independently executed, the processing flow being a flow in which a substrate is carried to a processing station from a cassette station to be processed in the processing station and an aligner and thereafter is returned to the cassette station, and the inspection flow being a flow in which the substrate is carried from the cassette station to an inspection station to be inspected there, and is thereafter returned to the cassette station.

Abstract: A coating and developing apparatus having a plurality of cassettes includes at least a step of acquiring, for each of all wafers retained in the cassettes, wafer attribute information associated with a cassette retaining that wafer and a process recipe, a step of acquiring inside-cassette information associated with the retained wafer, a step of acquiring information on a process recipe in an exposure apparatus directly from the exposure apparatus, and a step of determining a processing order for the plurality of wafers based on the attribute information, the inside-cassette information, process recipe information of the coating and developing apparatus which the coating and developing apparatus has, and the process recipe information of the exposure apparatus acquired from the exposure apparatus.

Abstract: In an equalizing filter circuit having an input terminal 101, an output terminal 102, delay devices 104 connected in multi-stage to the input terminal 101, and a plurality of weighting circuits 105 which are branched from and connected to the plurality of delay devices to thereby combine respective output signals of the weighting circuits, gain adjustment of the weighting circuits is performed to determine a coefficient of the equalizing filter circuit without depending on a load connected to the output terminal. Thus, an amount of compensation for a distorted waveform may be enhanced. To this end, an impedance converting circuit 108 is connected between at least one weighting circuit and the output terminal.

Abstract: A voltage controlled oscillator of the present invention includes power supply terminal (101), control terminal (2) for controlling an output frequency, output terminals (3a, 3b), cross-coupled transistors (5a, 5b), capacitances (6a, 6b, 7a, 7b), LC tanks (10a, 10b), resistor (117), grounding capacitance (18) and center frequency control circuit (16). Center frequency control circuit (16) includes resistors (11a, 11b), grounding capacitance (12), center frequency control terminal (4) for controlling a center frequency of the output frequency, and voltage-divider circuit (15). Resistors (11a, 11b) are connected to the base terminals of cross-coupled transistors (5a, 5b), the other ends of resistors (11a, 11b) are connected to each other, and, to this connecting point, one end of grounding capacitance (12) and one end of voltage-divider circuit (15) are connected. The other end of voltage-divider circuit (15) is connected to center frequency control terminal (4).

Abstract: Disclosed is a clock and data recovery circuit for improving the tracking speed against fluctuations or variations in a received data signal, and the clock quality, and for allowing automatic adjustment to an optimum phase of discrimination.

Abstract: It is an object of the present invention to realize, in a coating and developing apparatus including an inspection section, reduction in the startup time, cost reduction, and an improved operating rate of the inspection section. In the present invention, a control program of the coating and developing apparatus is set such that a processing flow and an inspection flow can be independently executed, the processing flow being a flow in which a substrate is carried to a processing station from a cassette station to be processed in the processing station and an aligner and thereafter is returned to the cassette station, and the inspection flow being a flow in which the substrate is carried from the cassette station to an inspection station to be inspected there, and is thereafter returned to the cassette station.

Abstract: A separation circuit part is used to separate an amplified signal path from a feedback signal path. An amplifier circuit part comprises a resistor-loaded common-source FET, a level adjustment diode and a source-follower circuit. The separation circuit part comprises a source-follower circuit, an output part of which is connected to a feedback circuit part comprising a resistor, thereby forming a feedback signal path to an input terminal of the amplifier circuit part. The signal separation circuit is used to separate the amplified signal path from the feedback signal path, thereby reducing the loads of the signal paths. In this way, the loads of the amplified signal and feedback signal paths are reduced.

Abstract: It at least includes a step at which a coating and developing apparatus requests an exposure apparatus, connected inline thereto, to transfer profile information which is information relating to the exposure apparatus, a step at which the coating and developing apparatus receives the profile information from the exposure apparatus, and a step at which the coating and developing apparatus selects a software file to be used in the coating and developing apparatus, in association with the profile information.

Abstract: A coating and developing apparatus having a plurality of cassettes includes at least a step of acquiring, for each of all wafers retained in the cassettes, wafer attribute information associated with a cassette retaining that wafer and a process recipe, a step of acquiring inside-cassette information associated with the retained wafer, a step of acquiring information on a process recipe in an exposure apparatus directly from the exposure apparatus, and a step of determining a processing order for the plurality of wafers based on the attribute information, the inside-cassette information, process recipe information of the coating and developing apparatus which the coating and developing apparatus has, and the process recipe information of the exposure apparatus acquired from the exposure apparatus.

Abstract: It at least includes a step at which a coating and developing apparatus requests an exposure apparatus, connected inline thereto, to transfer profile information which is information relating to the exposure apparatus, a step at which the coating and developing apparatus receives the profile information from the exposure apparatus, and a step at which the coating and developing apparatus selects a software file to be used in the coating and developing apparatus, in association with the profile information.

Abstract: A resist coating/developing system comprises a cassette station, a process station, and an interface station. A second wafer transfer member for transferring the wafer from a high precision temperature control unit mounted to the interface station to an in-stage of a light exposure device provisionally disposes the wafer held by the second wafer transfer member on a restoration unit in the case where the wafer was taken out from the high precision temperature control unit because it was possible to transfer the wafer onto the in-stage, but it was rendered impossible later to transfer the wafer W onto the in-stage.

Abstract: A separation circuit part is used to separate an amplified signal path from a feedback signal path. An amplifier circuit part comprises a resistor-loaded common-source FET, a level adjustment diode and a source-follower circuit. The separation circuit part comprises a source-follower circuit, an output part of which is connected to a feedback circuit part comprising a resistor, thereby forming a feedback signal path to an input terminal of the amplifier circuit part. The signal separation circuit is used to separate the amplified signal path from the feedback signal path, thereby reducing the loads of the signal paths. In this way, the loads of the amplified signal and feedback signal paths are reduced.