Patents by Inventor Shigemasa Ito
Shigemasa Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7995414Abstract: A semiconductor memory device is provided which comprises: a sense amplifier; and a bit line, wherein the disconnection of the sense amplifier from the bit line is performed in a data read operation when temperature in the semiconductor memory device is at a first temperature, and wherein the disconnection of the sense amplifier from the bit line is not performed in the data read operation when the temperature in the semiconductor memory device is at a second temperature.Type: GrantFiled: March 25, 2009Date of Patent: August 9, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Shigemasa Ito
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Publication number: 20090245003Abstract: A semiconductor memory device is provided which comprises: a sense amplifier; and a bit line, wherein the disconnection of the sense amplifier from the bit line is performed in a data read operation when temperature in the semiconductor memory device is at a first temperature, and wherein the disconnection of the sense amplifier from the bit line is not performed in the data read operation when the temperature in the semiconductor memory device is at a second temperature.Type: ApplicationFiled: March 25, 2009Publication date: October 1, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Shigemasa ITO
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Patent number: 7315481Abstract: When it is judged that real bit lines connected to real memory cells are liable to be connected to adjacent circuit elements to be electrically short-circuited, dummy bit lines are connected to voltage lines which supply voltages to the circuit elements. For example, the dummy bit lines are directly connected to a negative voltage line via a connection wiring line. Alternatively, the dummy bit lines are selectively connected to any one of internal voltage lines. Even when the dummy bit lines are connected to the adjacent circuit elements to be electrically short-circuited, a leak can be prevented from occurring between the dummy bit lines and the circuit elements. Since the leak can be prevented, internal voltage generators can be prevented from uselessly operating and a standby current can be prevented from increasing. As a result, the yield of the semiconductor memory can be enhanced.Type: GrantFiled: June 29, 2005Date of Patent: January 1, 2008Assignee: Fujitsu LimitedInventor: Shigemasa Ito
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Patent number: 7286434Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.Type: GrantFiled: July 14, 2006Date of Patent: October 23, 2007Assignee: Fujitsu LimitedInventors: Kaoru Mori, Katuhiro Mori, Shinichi Yamada, Kuninori Kawabata, Shigemasa Ito
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Patent number: 7227801Abstract: A semiconductor memory device includes a plurality of first fuse latch circuits configured to provide redundancy to first addresses, a plurality of second fuse latch circuits configured to provide redundancy to second addresses, and a nullifying circuit configured to make the plurality of second fuse latch circuits ineffective, wherein first fuse positions corresponding to the plurality of first fuse latch circuits intervene between second fuse positions corresponding to the plurality of second fuse latch circuits.Type: GrantFiled: April 25, 2005Date of Patent: June 5, 2007Assignee: Fujitsu LimitedInventors: Akira Kikutake, Shigemasa Ito, Kuninori Kawabata
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Patent number: 7145825Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.Type: GrantFiled: March 16, 2004Date of Patent: December 5, 2006Assignee: Fujitsu LimitedInventors: Kaoru Mori, Katuhiro Mori, Shinichi Yamada, Kuninori Kawabata, Shigemasa Ito
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Publication number: 20060256638Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.Type: ApplicationFiled: July 14, 2006Publication date: November 16, 2006Inventors: Kaoru Mori, Katuhiro Mori, Shinichi Yamada, Kuninori Kawabata, Shigemasa Ito
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Publication number: 20060203588Abstract: When it is judged that real bit lines connected to real memory cells are liable to be connected to adjacent circuit elements to be electrically short-circuited, dummy bit lines are connected to voltage lines which supply voltages to the circuit elements. For example, the dummy bit lines are directly connected to a negative voltage line via a connection wiring line. Alternatively, the dummy bit lines are selectively connected to any one of internal voltage lines. Even when the dummy bit lines are connected to the adjacent circuit elements to be electrically short-circuited, a leak can be prevented from occurring between the dummy bit lines and the circuit elements. Since the leak can be prevented, internal voltage generators can be prevented from uselessly operating and a standby current can be prevented from increasing. As a result, the yield of the semiconductor memory can be enhanced.Type: ApplicationFiled: June 29, 2005Publication date: September 14, 2006Inventor: Shigemasa Ito
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Publication number: 20050190618Abstract: A semiconductor memory device includes a plurality of first fuse latch circuits configured to provide redundancy to first addresses, a plurality of second fuse latch circuits configured to provide redundancy to second addresses, and a nullifying circuit configured to make the plurality of second fuse latch circuits ineffective, wherein first fuse positions corresponding to the plurality of first fuse latch circuits intervene between second fuse positions corresponding to the plurality of second fuse latch circuits.Type: ApplicationFiled: April 25, 2005Publication date: September 1, 2005Inventors: Akira Kikutake, Shigemasa Ito, Kuninori Kawabata
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Publication number: 20040184323Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.Type: ApplicationFiled: March 16, 2004Publication date: September 23, 2004Applicant: FUJITSU LIMITEDInventors: Kaoru Mori, Katuhiro Mori, Shinichi Yamada, Kuninori Kawabata, Shigemasa Ito
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Patent number: 6577550Abstract: A control circuit for increasing the speed of a device responding to a control request from an external device when the external control request is overlapped with an internal control request. The control circuit includes a first signal processing unit for receiving the first control signal and generating a first processed signal. The first signal processing unit includes a filter for filtering the first control signal. A second signal processing unit receives the first control signal and generates a second processed signal. An arbiter receives the second processed signal and the second control signal, determines which one of the received signals is to be given priority, and generates a determination signal based on the determination. A main signal generator generates the main signal from the determination signal or the first processed signal based on the determination signal.Type: GrantFiled: January 3, 2002Date of Patent: June 10, 2003Assignee: Fujitsu LimitedInventor: Shigemasa Ito
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Publication number: 20020145929Abstract: A control circuit for increasing the speed of a device responding to a control request from an external device when the external control request is overlapped with an internal control request. The control circuit includes a first signal processing unit for receiving the first control signal and generating a first processed signal. The first signal processing unit includes a filter for filtering the first control signal. A second signal processing unit receives the first control signal and generates a second processed signal. An arbiter receives the second processed signal and the second control signal, determines which one of the received signals is to be given priority, and generates a determination signal based on the determination. A main signal generator generates the main signal from the determination signal or the first processed signal based on the determination signal.Type: ApplicationFiled: January 3, 2002Publication date: October 10, 2002Applicant: Fujitsu LimitedInventor: Shigemasa Ito
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Publication number: 20020027829Abstract: A synchronous semiconductor memory apparatus is capable of activating an input buffer circuit only in a required operating cycle and achieving low current consumption without degrading high speed response properties of an input buffer. When combination of control signals (Control) such as ICS, /RAS, /CAS, /WE and the like is directed to active command (ACTV), read command (READ, READA), write command (WRITE, WRITEA), mode register command (MRS), pre-charge command (PRE) and the like, a latch operation is dynamically performed for input from address pins. In this way, in the case where a signal iRAS is set at a low level, a latch signal aCLK is output to the rising edge of a signal iCLK, thereby latching addresses Add or the like. Alternatively, in the case where a signal iRAS or iCAS is set at a low level, the latch signal aCLK is output to the rising edge of the signal iCLK, thereby latching addresses Add or the like.Type: ApplicationFiled: July 16, 2001Publication date: March 7, 2002Applicant: FUJITSU LIMITEDInventors: Mitsuhiro Higashiho, Shigemasa Ito
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Patent number: 6353565Abstract: A semiconductor device for reliably detecting an erroneous entry into a test mode in ordinary usage and for performing various operational tests at the time of shipment includes an internal circuit and a test-mode control circuit. The test-mode control circuit includes a first control circuit and a second control circuit. The test-mode control circuit operates the internal circuit in the test mode in accordance with a test mode command. The first control circuit inactivates at least a part of the internal circuit in accordance with the test mode command. The second control circuit activates at least the part of the internal circuit in accordance with a release command supplied following the test mode command.Type: GrantFiled: February 22, 2001Date of Patent: March 5, 2002Assignee: Fujitsu LimitedInventor: Shigemasa Ito
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Patent number: 6351432Abstract: A synchronous semiconductor memory apparatus is capable of activating an input buffer circuit only in a required operating cycle and achieving low current consumption without degrading high speed response properties of an input buffer. When combination of control signals (Control) such as /CS, /RAS, /CAS, /WE and the like is directed to active command (ACTV), read command (READ, READA), write command (WRITE, WRITEA), mode register command (MRS), pre-charge command (PRE) and the like, a latch operation is dynamically performed for input from address pins. In this way, in the case where a signal iRAS is set at a low level, a latch signal aCLK is output to the rising edge of a signal iCLK, thereby latching addresses Add or the like. Alternatively, in the case where a signal iRAS or iCAS is set at a low level, the latch signal aCLK is output to the rising edge of the signal iCLK, thereby latching addresses Add or the like.Type: GrantFiled: July 16, 2001Date of Patent: February 26, 2002Assignee: Fujitsu LimitedInventors: Mitsuhiro Higashiho, Shigemasa Ito
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Publication number: 20010017804Abstract: A semiconductor device for reliably detecting an erroneous entry into a test mode in ordinary usage and for performing various operational tests at the time of shipment includes an internal circuit and a test-mode control circuit. The test-mode control circuit includes a first control circuit and a second control circuit. The test-mode control circuit operates the internal circuit in the test mode in accordance with a test mode command. The first control circuit inactivates at least a part of the internal circuit in accordance with the test mode command. The second control circuit activates at least the part of the internal circuit in accordance with a release command supplied following the test mode command.Type: ApplicationFiled: February 22, 2001Publication date: August 30, 2001Applicant: FUJITSU LIMITEDInventor: Shigemasa Ito
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Patent number: 5675280Abstract: An LSI device can provide a desired constant value of a step-down voltage even if there are variations due to the production processes and a stable characteristic of internal circuits is obtained. The LSI device such as a DRAM includes a first input terminal of the high-voltage-side external supply voltage, a constant current source and a second input terminal of the low-voltage-side supply voltage. Further, the device includes a circuit which makes a voltage between two terminals variable due to the disconnection of each fuse. A step-down circuit is formed by the constant current source and the load circuit and provides a step-down voltage V.sub.B for stepping down the external supply voltage V.sub.CC.Type: GrantFiled: May 28, 1996Date of Patent: October 7, 1997Assignee: Fujitsu LimitedInventors: Yukihiro Nomura, Shigemasa Ito
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Patent number: 5499213Abstract: A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.Type: GrantFiled: June 29, 1993Date of Patent: March 12, 1996Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Makoto Niimi, Shigemasa Ito, Toyonobu Yamada, Yoshihiro Takemae, Yoshiharu Kato