Patents by Inventor Shigenobu Yamakoshi

Shigenobu Yamakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929402
    Abstract: A field-effect transistor includes a Ga2O3-based semiconductor layer, a source region and a drain region that are formed inside the Ga2O3-based semiconductor layer, a gate electrode that is formed, via a gate insulating film, on a channel region as the Ga2O3-based semiconductor layer between the source region and the drain region, a source electrode connected to the source region, and a drain electrode connected to the drain region. An interface charge including a negative charge is formed between the gate electrode and the channel region, and a gate threshold voltage is not less than 4.5V.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: March 12, 2024
    Assignee: Novel Crystal Technology, Inc.
    Inventors: Tadashi Kase, Kazuo Aoki, Shigenobu Yamakoshi, Yuki Uchida
  • Publication number: 20210273060
    Abstract: A field-effect transistor includes a Ga2O3-based semiconductor layer, a source region and a drain region that are formed inside the Ga2O3-based semiconductor layer, a gate electrode that is formed, via a gate insulating film, on a channel region as the Ga2O3-based semiconductor layer between the source region and the drain region, a source electrode connected to the source region, and a drain electrode connected to the drain region. An interface charge including a negative charge is formed between the gate electrode and the channel region, and a gate threshold voltage is not less than 4.5V.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 2, 2021
    Applicant: Novel Crystal Technology, Inc.
    Inventors: Tadashi KASE, Kazuo AOKI, Shigenobu YAMAKOSHI, Yuki UCHIDA
  • Patent number: 5001080
    Abstract: A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope facing the first gentle slope; an optical semiconductor element is constructed using the single crystalline layer. An electronic semiconductor element is constructed using the substrate surface. A wiring layer connects electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slopes.
    Type: Grant
    Filed: October 26, 1987
    Date of Patent: March 19, 1991
    Assignee: Fujitsu Limited of 1015
    Inventors: Osamu Wada, Tatsuyuki Sanada, Shuichi Miura, Hideki Machida, Shigenobu Yamakoshi, Teruo Sakurai
  • Patent number: 4719498
    Abstract: A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope facing the first gentle slope; an optical semiconductor element is constructed using the single crystalline layer. An electronic semiconductor element is constructed using the substrate surface. A wiring layer connects electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slopes.
    Type: Grant
    Filed: May 14, 1985
    Date of Patent: January 12, 1988
    Assignee: Fujitsu Limited
    Inventors: Osamu Wada, Tatsuyuki Sanada, Shuichi Miura, Hideki Machida, Shigenobu Yamakoshi, Teruo Sakurai
  • Patent number: 4630083
    Abstract: A transverse junction strip structure light-emitting semiconductor device (laser) includes a laminated active layer of a multiquantum well structure. A P-type region of the semiconductor device is formed by doping P-type impurities into portions of the active layer and the clad layers between which the active layer is sandwiched. The P-type region includes a mixture region which is formed by diffusing P-type impurities into first semiconductor ultrathin layers serving as wells and second semiconductor ultrathin layers serving as barriers. The mixture region has a larger band gap than the first semiconductor ultrathin layers and forms a heterojunction with the first semiconductor ultrathin layers.
    Type: Grant
    Filed: August 12, 1983
    Date of Patent: December 16, 1986
    Assignee: Fujitsu Limited
    Inventor: Shigenobu Yamakoshi