Patents by Inventor Shigenori ISOZAKI

Shigenori ISOZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230155567
    Abstract: A vibrator device has a base, a semiconductor element having an oscillation circuit, and a vibrator having an excitation electrode sequentially stacked and includes a first wire electrically coupling between the excitation electrode and the semiconductor element, a second wire electrically coupling between a second external terminal as an external output terminal placed on the base and the semiconductor element, and a shield wire placed between at least a part of the first wire and at least a part of the second wire.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 18, 2023
    Inventors: Shigenori Isozaki, Shinya Aoki
  • Patent number: 10461694
    Abstract: A circuit device includes an A/D conversion circuit that performs A/D conversion on a temperature detection voltage from a temperature sensor so as to output temperature detection data, and a digital signal processing circuit that performs a temperature compensation process on the basis of the temperature detection data, in which the A/D conversion circuit operates in a first mode, and switches to a second mode in a case where a predetermined condition is established.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 29, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Atsushi Kiyohara, Shinnosuke Kano, Shigenori Isozaki, Mihiro Nonoyama
  • Patent number: 10333491
    Abstract: An oscillator includes a package having a first side, a second side, a third side, and a fourth side, a resonator and an oscillation circuit disposed in the package, an output terminal arranged along the first side of the package, and outputting a clock signal generated by the oscillation circuit, and a control terminal arranged along the second side of the package, and supplied with a digital control signal adapted to update an operation state of the oscillation circuit.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: June 25, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Shigenori Isozaki, Akihiro Fukuzawa, Toshimasa Usui
  • Patent number: 10256824
    Abstract: A D/A converter includes a decoder, a voltage selection circuit, and a voltage selection circuit. The voltage selection circuit includes a plurality of stages of selector blocks in which output of a selector of the selector block at the previous stage is input to a selector of the selector block at the subsequent stage. A plurality of voltages are input to the selector block at the first stage, and the selector block at the final stage outputs a D/A-converted voltage. Each of the plurality of stages of selector blocks includes a plurality of transistors and, of the plurality of transistors forming the selector block, a second transistor on a far side from a power source node is set to a lower threshold voltage than that of a first transistor on a near side from the power source node.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 9, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Isozaki
  • Publication number: 20180241344
    Abstract: A circuit device includes an A/D conversion circuit that performs A/D conversion on a temperature detection voltage from a temperature sensor so as to output temperature detection data, and a digital signal processing circuit that performs a temperature compensation process on the basis of the temperature detection data, in which the A/D conversion circuit operates in a first mode, and switches to a second mode in a case where a predetermined condition is established.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 23, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Atsushi KIYOHARA, Shinnosuke KANO, Shigenori ISOZAKI, Mihiro NONOYAMA
  • Publication number: 20170170832
    Abstract: A D/A converter includes a decoder, a voltage selection circuit, and a voltage selection circuit. The voltage selection circuit includes a plurality of stages of selector blocks in which output of a selector of the selector block at the previous stage is input to a selector of the selector block at the subsequent stage. A plurality of voltages are input to the selector block at the first stage, and the selector block at the final stage outputs a D/A-converted voltage. Each of the plurality of stages of selector blocks includes a plurality of transistors and, of the plurality of transistors forming the selector block, a second transistor on a far side from a power source node is set to a lower threshold voltage than that of a first transistor on a near side from the power source node.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 15, 2017
    Inventor: Shigenori ISOZAKI
  • Publication number: 20170134004
    Abstract: An oscillator includes a package having a first side, a second side, a third side, and a fourth side, a resonator and an oscillation circuit disposed in the package, an output terminal arranged along the first side of the package, and outputting a clock signal generated by the oscillation circuit, and a control terminal arranged along the second side of the package, and supplied with a digital control signal adapted to update an operation state of the oscillation circuit.
    Type: Application
    Filed: November 7, 2016
    Publication date: May 11, 2017
    Inventors: Shigenori ISOZAKI, Akihiro FUKUZAWA, Toshimasa USUI
  • Patent number: 9515673
    Abstract: A D/A conversion circuit includes a plurality of resistors that are connected to each other in series, and a plurality of MOS transistors that are connected to terminals of the plurality of resistors, respectively. The plurality of resistors and the plurality of MOS transistors are formed on a semiconductor substrate. Each of the plurality of resistors is constituted by a resistive element and a plurality of contacts provided in the resistive element. The plurality of MOS transistors are disposed so that a plurality of virtual straight lines that pass through each of the plurality of contacts and are perpendicular to a longitudinal direction of the resistive element pass between gate electrodes of two adjacent MOS transistors, when seen in a plan view of the semiconductor substrate.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: December 6, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Isozaki
  • Patent number: 9432048
    Abstract: A D/A conversion circuit includes a plurality of resistors connected to each other in series, a plurality of MOS transistors connected to each other so as to correspond to a plurality of contacts, and a plurality of dummy electrodes respectively disposed on sides opposite to the plurality of MOS transistors with a resistive element interposed therebetween when seen in a plan view of a semiconductor substrate. Each of the dummy electrodes is set to be in a second potential state when a gate electrode of the MOS transistor disposed on a side opposite thereto with the resistive element interposed therebetween is in a first potential state, and is set to be in a first potential state when the gate electrode of the MOS transistor is in a second potential state.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: August 30, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Isozaki
  • Publication number: 20160211859
    Abstract: A D/A conversion circuit includes a plurality of resistors connected to each other in series, a plurality of MOS transistors connected to each other so as to correspond to a plurality of contacts, and a plurality of dummy electrodes respectively disposed on sides opposite to the plurality of MOS transistors with a resistive element interposed therebetween when seen in a plan view of a semiconductor substrate. Each of the dummy electrodes is set to be in a second potential state when a gate electrode of the MOS transistor disposed on a side opposite thereto with the resistive element interposed therebetween is in a first potential state, and is set to be in a first potential state when the gate electrode of the MOS transistor is in a second potential state.
    Type: Application
    Filed: January 14, 2016
    Publication date: July 21, 2016
    Inventor: Shigenori ISOZAKI
  • Publication number: 20160211860
    Abstract: A D/A conversion circuit includes a plurality of resistors that are connected to each other in series, and a plurality of MOS transistors that are connected to terminals of the plurality of resistors, respectively. The plurality of resistors and the plurality of MOS transistors are formed on a semiconductor substrate. Each of the plurality of resistors is constituted by a resistive element and a plurality of contacts provided in the resistive element. The plurality of MOS transistors are disposed so that a plurality of virtual straight lines that pass through each of the plurality of contacts and are perpendicular to a longitudinal direction of the resistive element pass between gate electrodes of two adjacent MOS transistors, when seen in a plan view of the semiconductor substrate.
    Type: Application
    Filed: January 14, 2016
    Publication date: July 21, 2016
    Inventor: Shigenori ISOZAKI