Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: A semiconductor apparatus comprises a semiconductor body of one conductivity type; a first impurity region of an opposite conductivity type, which is formed in the surface area of the semiconductor body; impurity regions of the opposite conductivity type, formed in the surface area of the semiconductor body, at locations away from the first impruity region; second and third impurity regions of one conductivity type, which seve as source and drain regions, respectively, and are formed in the impurity regions of an opposite conductivity type, so as to sandwich a channel reigon; and a gate electrode formed on the channel region, through an insulative layer. In this semiconductor apparatus, the impurity regions of the opposite conductivity type include fourth and fifth impurity regions, formed in the channel region such that at least parts of the fourth and fifth impurity regions overlap.

Abstract: A first short-circuiting MOS FET with a break-through preventing function is connected between the gate and the cathode of a high sensitivity thyristor. A second MOS FET is connected between the gate and the source of the first MOS FET. A gate signal turns on the second MOS FET to reduce the gate voltage of the first MOS FET below threshold voltage. In turn, the short-circuit of the gate to the cathode of the thyristor is removed. Specifically, the gate signal is applied to the gate of the thyristor to trigger it. When forward voltage VAK applied between the anode terminal and the cathode terminal of the thyristor element is larger than the threshold voltage of the first MOS FET, the gate of the first MOS FET is biased to a voltage above the threshold voltage so that the first MOS FET is turned on. Therefore, the gate and the cathode of the thyristor element are short-circuited to prevent the break-through of the thyristor due to the an external transient surge voltage.

Abstract: A MOSFET is provided between a main thyristor and an auxiliary thyristor for controlling the main thyristor. The source and drain regions of the MOSFET are also used as a first N-type emitter region of the main thyristor and a second N-type emitter region of the auxiliary thyristor. The MOSFET and the auxiliary thyristor are controlled by an output of a gate energization circuit. When the MOSFET is turned on by an output of the gate energization circuit, the main thyristor is connected to the auxiliary thyristor. At this time, the auxiliary thyristor is turned on by the output of the gate energization circuit, and the main thyristor is also turned on due to the turn-on operation of the auxiliary thyristor. When the MOSFET is in the OFF state, the main thyristor is electrically isolated from the auxiliary thyristor.

Abstract: A zero-cross thyristor comprises an n-type substrate region surrounded by a p-type region, a p-type base region formed in the n-type substrate region and surrounding an n-type inner region of the n-type substrate region, and a p-type floating region formed in the n-type inner region. An n-channel MOS transistor whose gate is connected to the floating region is formed in the p-type base region. A first p.sup.+ -type diffusion region whose depth is less than that of the p-type base region is continuously formed in the p-type base region and the n-type inner region and a second p.sup.+ -type diffusion region whose depth is also less than that of the p-type floating region. The distance between the first and second diffusion regions is set to a predetermined value for preventing the breakdown of the gate insulating layer of the MOS transistor.

Abstract: In a thyristor to which a semiconductor device according to the present invention is applied, at least one p-n junction is exposed at one surface of a semiconductor substrate, a polysilicon field plate is formed, via an insulating film, over the p-n junction of the semiconductor substrate and a gate region formed therein, so that the exposed portion of the p-n junction is covered by the field plate, and two specific regions of the field plate are electrically connected to the gate region and cathode region to form a gate-cathode resistance between the gate region and the cathode region. The resistance of the polysilicon field plate, inserted between the gate region and the cathode region, can be determined by the length of the polysilicon field plate therebetween and/or the concentration of an impurity in the polysilicon field plate therebetween.

Abstract: A low-loss P-i-n diode includes an i-type layer consisting of first and second i-type regions formed on the cathode layer of the diode and the i-type has a thickness W.sub.i of less than 25 .mu.m. The impurity concentration of the first i-type region is higher than that of the second i-type region. To obtain a good forward-voltage V.sub.f, W.sub.i.sup.2 /.tau. is selected to be in the range of 20-200cm.sup.cm.sup.2/sec and the carrier lifetime .tau. of the i-type layer is controlled by a carrier lifetime killer with a small resistivity compensation effect which is diffused into the i-type layer. The P-i-n diode has a high reverse breakdown voltage, small forward-voltage drop and a short recovery time.