Patents by Inventor Shigeo Hagiya

Shigeo Hagiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6268646
    Abstract: A lead frame for LOC to which a semiconductor chip is fixed within a semiconductor chip-mounting region. In addition to applying insulative adhesives to the conventional portions or spots which are on the bottom surfaces of the leading edges of respective inner leads for wire bonding to the pads for the semiconductor ship, the insulative adhesives are applied to other portions of the inner leads in the vicinity of the semiconductor chip-mounting region. Accordingly, the area for bonding the semiconductor chip can be enlarged resulting in improvements in the stability of adhesion between the leads and the semiconductor chip, and in the stabilities of wire bonding and resin molding.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: July 31, 2001
    Assignee: Hitachi Cable, Ltd.
    Inventors: Hiroshi Sugimoto, Shigeo Hagiya, Noriaki Taketani, Takaharu Yonemoto, Osamu Yoshioka
  • Patent number: 6246106
    Abstract: A lead frame is provided which enables a coating of an insulating adhesive for fixing a semiconductor chip to be evenly and thickly foamed on inner leads. In a lead frame wherein an insulating adhesive for fixing a semiconductor chip is applied to a semiconductor chip mounting region, inner leads 1 are set to a value of w/s of not more than 1 wherein w represents the lead width and s represents the lead spacing.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: June 12, 2001
    Assignee: Hitachi Cable, Ltd.
    Inventors: Hiroshi Sugimoto, Shigeo Hagiya, Noriaki Taketani, Takaharu Yonemoto, Osamu Yoshioka
  • Patent number: 6107675
    Abstract: A lead frame for semiconductor device comprises first inner leads 21-2, 21-3 and 21-4 each having a region 22-2, 22-3, 22-4 on which a predetermined quantity of adhesive is applied, and second inner leads 21-1 and 21-5 each having a region 22-1, 22-5 which is wider than those of the first inner leads. The first inner leads 21-2, 21-3 and 21-4 have a width W.sub.1, while the second inner leads 21-1 and 21-5 have a width W.sub.2 which is wider than W1. The second inner leads 21-1 and 21-5 are arranged at the positions where one successive application of varnish-like adhesive to the inner leads begins and ends, respectively. The ratio of W.sub.1 to W.sub.2 is preferably 1 to 1.3 (i.e., W.sub.1 :W.sub.2 =1:1.3) or more. Even if an excessive quantity of varnish-like adhesive is applied to the beginning inner lead 21-1 or the ending inner lead 21-5, it is spread over the region 22-1 or 22-5, then adhesive layers having uniform thickness are formed.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: August 22, 2000
    Assignee: Hitachi Cable, Ltd.
    Inventors: Hiroshi Sugimoto, Hiroki Tanaka, Shigeo Hagiya, Takaharu Yonemoto
  • Patent number: 6040620
    Abstract: A lead frame for LOC is provided which can reduce a variation in coverage of an insulating adhesive, permitting the fixation of a semiconductor chip and wire bonding to be stably performed. In a lead frame for LOC 10 wherein an insulating adhesive for fixing a semiconductor chip is applied to inner leads 11 in their semiconductor chip mounting region, a coverage regulating lead 14 is provided outside the semiconductor chip mounting region and adjacent to inner leads 11a, 11b located at the end of the semiconductor chip mounting region, permitting the insulting adhesive to be homogeneously applied to each of the inner leads 11 without creating any variation in coverage of the adhesive.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: March 21, 2000
    Assignee: Hitachi Cable, Ltd.
    Inventors: Hiroshi Sugimoto, Shigeo Hagiya, Noriaki Taketani, Takaharu Yonemoto, Osamu Yoshioka
  • Patent number: 5880522
    Abstract: A lead frame for LOC is provided which, even when an adhesive is applied to a lead prepared by stamping, can ensure insulation of a semiconductor element mounted from the lead. In applying an adhesive to a predetermined position of an inner lead 1 in a lead frame prepared by stamping to form an adhesive layer 4, the adhesive layer 4 is provided on the droop face of the inner lead 1. The droop face has no burr and a bulged center portion, permitting contact, derived from the burr, between a lead face and a semiconductor element, to be avoided, which ensures satisfactory insulation of the semiconductor element mounted from the lead.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: March 9, 1999
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takaharu Yonemoto, Hiroshi Sugimoto, Shigeo Hagiya, Noriaki Taketani, Osamu Yoshioka